[Commit-gnuradio] r5032 - gnuradio/branches/developers/matt/u2f/boot_cpld

[matt]

Author: matt
Date: 2007-04-17 02:07:33 -0600 (Tue, 17 Apr 2007)
New Revision: 5032

Modified:
   gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ise
   gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v
Log:
partially integrated the opencore spi boot logic


Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v 2007-04-17 
08:06:24 UTC (rev 5031)
+++ gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v 2007-04-17 
08:07:33 UTC (rev 5032)
@@ -26,39 +26,82 @@
    input CLK_25MHZ;
    output CLK_25MHZ_EN;
    output [2:0] LED;
-   output      SPI_CPLD_CLK;   // temporary, for clock bootstrapping
-   input       SPI_CPLD_DIN;
-   input       SPI_CPLD_DOUT;
-   input       SPI_CPLD_EN;
-   input       SD_nCS;
-   input       SD_Din;
-   input       SD_CLK;
-   input       SD_Dout;
-   input       SD_DAT1;
-   input       SD_DAT2;
-   input       CFG_INIT_B;
-   input       CFG_Din;
    output [10:0] DEBUG;
    input        POR;
-   input        CFG_CCLK;
+   
+   // To FPGA data interface
+   output       SPI_CPLD_CLK;   // temporary, for clock bootstrapping
+   input        SPI_CPLD_DIN;
+   input        SPI_CPLD_DOUT;
+   input        SPI_CPLD_EN;
+   
+   // To SD Card
+   output       SD_nCS;
+   output       SD_Din;
+   output       SD_CLK;
+   input        SD_Dout;
+   input        SD_DAT1;  // Unused
+   input        SD_DAT2;  // Unused
+   
+   // To FPGA Config Interface
+   input        CFG_INIT_B;
+   output       CFG_Din;
+   output       CFG_CCLK;
    input        CFG_DONE;
-   input        CFG_PROG_B;
-
+   output       CFG_PROG_B;
+   
    assign       CLK_25MHZ_EN = 1'b1;
+   
+   assign       LED[0] = 1'b0;
+   assign       LED[1] = 1'b1;
+   assign       LED[2] = 1'b0;
+   
+   assign       SPI_CPLD_CLK = CLK_25MHZ;
 
-   reg [23:0]   counter;
+   wire         start, mode, detached, dat_done, en_outs;
+   wire [3:0]   set_sel = 4'd0;
 
-   always @(posedge CLK_25MHZ)
-     counter <= #1 counter + 24'd1;
+   assign       debug = { /* start, mode,*/ detached, dat_done, 
+                         SD_CLK, SD_nCS, SD_Dout, SD_Din, 
+                         CFG_PROG_B, CFG_INIT_B, CFG_DONE, CFG_CCLK, CFG_Din};
 
-   assign       LED[0] = 1'b0;
-   assign       LED[1] = 1'b0;
-   assign       LED[2] = counter[23];
-
-   assign       DEBUG = counter[23:13];
-
-   assign       SPI_CPLD_CLK = CLK_25MHZ;
+   //  Control signals, need to figure out how to drive these
+   assign       start = SPI_CPLD_DOUT;   // This is the important one
+   assign       dat_done = SPI_CPLD_DIN;
+   assign       mode = SPI_CPLD_EN;
+        
+   spi_boot #(.width_set_sel_g(4),  // How many sets (16)
+             .width_bit_cnt_g(6),  // Block length (12 is faster, 6 is minimum)
+             .width_img_cnt_g(2),  // How many images per set
+             .num_bits_per_img_g(18), // 256 kb Image size, probably needs to 
be bigger than 18
+             .sd_init_g(1),           // SD-specific initialization
+             .mmc_compat_clk_div_g(0),// No MMC support
+             .width_mmc_clk_div_g(0), // No MMC support
+             .reset_level_g(0))       // Active low reset
+     
+     spi_boot(.clk_i(CLK_25MHZ), 
+             .reset_i(POR),
+             
+             // To SD Card
+             .spi_clk_o(SD_CLK), 
+             .spi_cs_n_o(SD_nCS),
+             .spi_data_in_i(SD_Dout), 
+             .spi_data_out_o(SD_Din), 
+             .spi_en_outs_o(en_outs), 
+             
+             // Data Port
+             .start_i(start),
+             .mode_i(mode), // 0->conf mode, 1->data mode  
+             .detached_o(detached), 
+             .dat_done_i(dat_done), 
+             .set_sel_i(set_sel),
+             
+             // To FPGA
+             .config_n_o(CFG_PROG_B), 
+             .cfg_init_n_i(CFG_INIT_B), 
+             .cfg_done_i(CFG_DONE), 
+             .cfg_clk_o(CFG_CCLK), 
+             .cfg_dat_o(CFG_Din)
+             );
    
-
 endmodule // boot_cpld
-