[Commit-gnuradio] r5061 - gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib

[thottelt]

Author: thottelt
Date: 2007-04-21 11:03:27 -0600 (Sat, 21 Apr 2007)
New Revision: 5061

Modified:
   gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/tx_buffer.v
Log:
restore tx_buffer

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/tx_buffer.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/tx_buffer.v  
2007-04-21 00:36:46 UTC (rev 5060)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/tx_buffer.v  
2007-04-21 17:03:27 UTC (rev 5061)
@@ -32,11 +32,10 @@
     output wire have_space,
     output reg tx_underrun,
     input wire [3:0] channels,
-    output [15:0] tx_i_0,
-    output [15:0] tx_q_0,
-    output [15:0] tx_i_1,
-    output [15:0] tx_q_1,
-    //NOT USED
+    output reg [15:0] tx_i_0,
+    output reg [15:0] tx_q_0,
+    output reg [15:0] tx_i_1,
+    output reg [15:0] tx_q_1,
     output reg [15:0] tx_i_2,
     output reg [15:0] tx_q_2,
     output reg [15:0] tx_i_3,
@@ -47,67 +46,8 @@
     output wire tx_empty,
     output [11:0] debugbus
     );
-
-   wire [15:0] tx_data_bus;
-   //TODO: increment it
-   reg [31:0] time_counter;
-
-   wire WR_chan_0;
-   wire chan_0_done;
-   wire OR0;
-   wire UR0;
    
-   wire WR_chan_1;
-   wire chan_1_done;
-   wire OR1;
-   wire UR1;
-   
-   // NOT USED yet
-   wire WR_cmd;
-   wire cmd_done;
-   
-       usb_fifo_reader usb_reader (
-               .reset(reset),
-               .usb_clock(usbclk),
-               .WR(WR),
-               .tx_clock(txclk),
-               .tx_data_bus(tx_data_bus),
-      .WR_chan_0(WR_chan_0),
-      .WR_chan_1(WR_chan_1),
-      .WR_cmd(WR_cmd),
-      .chan_0_done(chan_0_done),
-      .chan_1_done(chan_1_done),
-      .cmd_done(cmd_done),
-               .usb_data(usbdata)
-       );
-
-   chan_fifo_reader chan_0_reader (
-      .reset(reset),
-      .tx_clock(txclk),
-      .adc_clock(time_counter),
-      .data_bus(tx_data_bus),
-      .WR(WR_chan_0),
-      .pkt_complete(chan_0_done),
-      .tx_q(tx_q_0),
-      .tx_i(tx_i_0),
-      .overrun(OR0),
-      .underrun(UR0)
-   );  
-   
-   chan_fifo_reader chan_1_reader (
-      .reset(reset),
-      .tx_clock(txclk),
-      .adc_clock(time_counter),
-      .data_bus(tx_data_bus),
-      .WR(WR_chan_1),
-      .pkt_complete(chan_1_done),
-      .tx_q(tx_q_1),
-      .tx_i(tx_i_1),
-      .overrun(OR1),
-      .underrun(UR1)
-   );  
-
-   /*wire [11:0] txfifolevel;
+   wire [11:0] txfifolevel;
    reg [8:0] write_count;
    wire tx_full;
    wire [15:0] fifodata;
@@ -192,7 +132,7 @@
    assign debugbus[5] = write_count[8];
    assign debugbus[6] = txstrobe;
    assign debugbus[7] = rdreq;
-   assign debugbus[11:8] = load_next;*/
+   assign debugbus[11:8] = load_next;
    
 endmodule // tx_buffer