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[Commit-gnuradio] r5062 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5062 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga inband/usrp/fpga/inband_lib inband/usrp/fpga/sdr_lib simulations |
|
Date: |
Sat, 21 Apr 2007 11:15:14 -0600 (MDT) |
Author: thottelt
Date: 2007-04-21 11:15:14 -0600 (Sat, 21 Apr 2007)
New Revision: 5062
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo.v
Removed:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
Modified:
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
Log:
cleaned up the mess I made
Copied:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
(from rev 5053,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v)
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-04-21 17:15:14 UTC (rev 5062)
@@ -0,0 +1,174 @@
+module chan_fifo_reader
+ ( input reset,
+ input tx_clock,
+ input [31:0]adc_clock,
+ input [15:0]data_bus,
+ input WR,
+ input pkt_complete,
+ output reg [15:0]tx_q,
+ output reg [15:0]tx_i,
+ output reg overrun,
+ output reg underrun) ;
+
+ // States
+ `define IDLE 4'd0
+ `define READ 4'd1
+ `define HEADER1 4'd2
+ `define HEADER2 4'd3
+ `define TIMESTAMP1 4'd4
+ `define TIMESTAMP2 4'd5
+ `define WAIT 4'd6
+ `define SENDWAIT 4'd7
+ `define SEND 4'd8
+ `define DISCARD 4'd9
+
+ // fifo inputs
+ reg skip;
+ reg rdreq;
+
+ // fifo ouputs
+ wire [15:0] fifodata;
+ wire pkt_waiting;
+
+ // Channel fifo
+ data_packet_fifo tx_usb_fifo
+ ( .reset(reset),
+ .clock_in(tx_clock),
+ .clock_out(tx_clock),
+ .ram_data_in(data_bus),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .pkt_complete(pkt_complete),
+ .skip_packet(skip)
+ );
+
+ // State registers
+ reg[3:0] reader_state;
+ reg[3:0] reader_next_state;
+
+ //Variables
+ reg[8:0] payload_len;
+ reg[8:0] read_len;
+ reg[31:0] timestamp;
+ reg burst;
+
+ always @(posedge tx_clock)
+ begin
+ if (reset)
+ begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ overrun <= 0;
+ underrun <= 0;
+ burst <= 0;
+ end
+ else
+ begin
+ reader_state = reader_next_state;
+ case (reader_state)
+ `IDLE:
+ begin
+ reader_next_state <= pkt_waiting ? `READ : `IDLE;
+ rdreq <= pkt_waiting;
+ end
+
+ // Just wait for the fifo data to arrive
+ `READ:
+ begin
+ reader_next_state <= `HEADER1;
+ end
+
+ // First part of the header nothing usefull
+ `HEADER1:
+ begin
+ reader_next_state <= `HEADER2;
+ end
+
+ // Read payload length
+ `HEADER2:
+ begin
+ payload_len <= (fifodata & 16'h1FF);
+ read_len <= 9'd0;
+ reader_next_state <= `TIMESTAMP1;
+ end
+
+ `TIMESTAMP1:
+ begin
+ timestamp <= {fifodata, 16'b0};
+ rdreq <= 0;
+ reader_next_state <= `TIMESTAMP2;
+ end
+
+ `TIMESTAMP2:
+ begin
+ timestamp <= timestamp + fifodata;
+ reader_next_state <= `WAIT;
+ end
+
+ // Decide if we wait, send or discard samples
+ `WAIT:
+ begin
+ // Wait a little bit more
+ if (timestamp > adc_clock + 5)
+ reader_next_state <= `WAIT;
+ // Prepare to send
+ else if (timestamp < adc_clock + 5
+ && timestamp > adc_clock)
+ begin
+ reader_next_state <= `SENDWAIT;
+ rdreq <= 1;
+ end
+ // Outdated
+ else if (timestamp < adc_clock)
+ begin
+ reader_next_state <= `DISCARD;
+ skip <= 1;
+ end
+ end
+
+ `SENDWAIT:
+ begin
+ reader_next_state <= `SEND;
+ end
+
+ // Send the samples to the tx_chain
+ `SEND:
+ begin
+ read_len <= read_len + 2;
+
+ // If end of payload...
+ if (read_len == payload_len)
+ begin
+ reader_next_state <= `DISCARD;
+ skip <= (payload_len < 508);
+ end
+ else
+ begin
+ if (read_len == payload_len - 4)
+ rdreq <= 0;
+ // Forward data
+ tx_q <= fifodata;
+ end
+ end
+
+ `DISCARD:
+ begin
+ skip <= 0;
+ reader_next_state <= `IDLE;
+ end
+
+ default:
+ begin
+ $display ("Error unknown state");
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ end
+ endcase
+ end
+ end
+
+endmodule
\ No newline at end of file
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
2007-04-21 17:15:14 UTC (rev 5062)
@@ -0,0 +1,109 @@
+module data_packet_fifo
+ ( input reset,
+ input clock_in,
+ input clock_out,
+ input [15:0]ram_data_in,
+ input write_enable,
+ output reg [15:0]ram_data_out,
+ output reg pkt_waiting,
+ input read_enable,
+ input pkt_complete,
+ input skip_packet) ;
+
+ /* Some parameters for usage later on */
+ parameter DATA_WIDTH = 16 ;
+ parameter NUM_PACKETS = 4 ;
+
+ /* Create the RAM here */
+ reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
+
+ /* Create the address signals */
+ reg [7:0] usb_ram_offset_out ;
+ reg [1:0] usb_ram_packet_out ;
+ reg [7:0] usb_ram_offset_in ;
+ reg [1:0] usb_ram_packet_in ;
+
+ wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
+ wire [7-2+NUM_PACKETS:0] usb_ram_ain ;
+
+ assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
+ assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
+
+ // Check if there is one full packet to process
+ always @(usb_ram_ain, usb_ram_aout)
+ begin
+ if (reset)
+ pkt_waiting <= 0;
+ else if (usb_ram_ain >= usb_ram_aout)
+ pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
+ else
+ pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >=
256;
+ end
+
+ /* RAM Write Address process */
+ always @(posedge clock_in)
+ begin
+ if( reset )
+ begin
+ usb_ram_offset_in <= 0 ;
+ usb_ram_packet_in <= 0 ;
+ end
+ else
+ if( pkt_complete )
+ begin
+ usb_ram_packet_in <= usb_ram_packet_in + 1;
+ usb_ram_offset_in <= 0;
+ end
+ else if( write_enable )
+ begin
+ if (usb_ram_offset_in == 8'b11111111)
+ begin
+ usb_ram_offset_in <= 0;
+ usb_ram_packet_in <= usb_ram_packet_in + 1;
+ end
+ else
+ usb_ram_offset_in <= usb_ram_offset_in + 1 ;
+ end
+ end
+
+ /* RAM Writing process */
+ always @(posedge clock_in)
+ begin
+ if( write_enable )
+ begin
+ usb_ram[usb_ram_ain] <= ram_data_in ;
+ end
+ end
+
+ /* RAM Read Address process */
+ always @(posedge clock_out)
+ begin
+ if( reset )
+ begin
+ usb_ram_packet_out <= 0 ;
+ usb_ram_offset_out <= 0 ;
+ end
+ else
+ if( skip_packet )
+ begin
+ usb_ram_packet_out <= usb_ram_packet_out + 1 ;
+ usb_ram_offset_out <= 0 ;
+ end
+ else if(read_enable) begin
+ if( usb_ram_offset_out == 8'b11111111 )
+ begin
+ usb_ram_offset_out <= 0 ;
+ usb_ram_packet_out <= usb_ram_packet_out + 1 ;
+ end
+ else
+ usb_ram_offset_out <= usb_ram_offset_out + 1 ;
+ end
+ end
+
+ /* RAM Reading Process */
+ always @(posedge clock_out)
+ begin
+ ram_data_out <= usb_ram[usb_ram_aout] ;
+ end
+
+endmodule
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/data_packet_fifo.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer.v
2007-04-21 17:15:14 UTC (rev 5062)
@@ -0,0 +1,111 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+// Interface to Cypress FX2 bus
+// A packet is 512 Bytes. Each fifo line is 2 bytes
+// Fifo has 1024 or 2048 lines
+
+module tx_buffer
+ ( input usbclk,
+ input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
+ input reset, // standard DSP-side reset
+ input [15:0] usbdata,
+ input wire WR,
+ output wire have_space,
+ output reg tx_underrun,
+ input wire [3:0] channels,
+ output [15:0] tx_i_0,
+ output [15:0] tx_q_0,
+ output [15:0] tx_i_1,
+ output [15:0] tx_q_1,
+ //NOT USED
+ output reg [15:0] tx_i_2,
+ output reg [15:0] tx_q_2,
+ output reg [15:0] tx_i_3,
+ output reg [15:0] tx_q_3,
+ input txclk,
+ input txstrobe,
+ input clear_status,
+ output wire tx_empty,
+ output [11:0] debugbus
+ );
+
+ wire [15:0] tx_data_bus;
+ //TODO: increment it
+ reg [31:0] time_counter;
+
+ wire WR_chan_0;
+ wire chan_0_done;
+ wire OR0;
+ wire UR0;
+
+ wire WR_chan_1;
+ wire chan_1_done;
+ wire OR1;
+ wire UR1;
+
+ // NOT USED yet
+ wire WR_cmd;
+ wire cmd_done;
+
+ usb_fifo_reader usb_reader (
+ .reset(reset),
+ .usb_clock(usbclk),
+ .WR(WR),
+ .tx_clock(txclk),
+ .tx_data_bus(tx_data_bus),
+ .WR_chan_0(WR_chan_0),
+ .WR_chan_1(WR_chan_1),
+ .WR_cmd(WR_cmd),
+ .chan_0_done(chan_0_done),
+ .chan_1_done(chan_1_done),
+ .cmd_done(cmd_done),
+ .usb_data(usbdata)
+ );
+
+ chan_fifo_reader chan_0_reader (
+ .reset(reset),
+ .tx_clock(txclk),
+ .adc_clock(time_counter),
+ .data_bus(tx_data_bus),
+ .WR(WR_chan_0),
+ .pkt_complete(chan_0_done),
+ .tx_q(tx_q_0),
+ .tx_i(tx_i_0),
+ .overrun(OR0),
+ .underrun(UR0)
+ );
+
+ chan_fifo_reader chan_1_reader (
+ .reset(reset),
+ .tx_clock(txclk),
+ .adc_clock(time_counter),
+ .data_bus(tx_data_bus),
+ .WR(WR_chan_1),
+ .pkt_complete(chan_1_done),
+ .tx_q(tx_q_1),
+ .tx_i(tx_i_1),
+ .overrun(OR1),
+ .underrun(UR1)
+ );
+
+endmodule // tx_buffer
+
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer.v
___________________________________________________________________
Name: svn:executable
+ *
Copied:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
(from rev 5053,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v)
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-04-21 17:15:14 UTC (rev 5062)
@@ -0,0 +1,171 @@
+module usb_fifo_reader (
+ input usb_clock,
+ input tx_clock,
+ input [15:0] usb_data,
+ input WR,
+ input reset,
+ output reg cmd_done,
+ output reg chan_0_done,
+ output reg chan_1_done,
+ output reg WR_cmd,
+ output reg WR_chan_0,
+ output reg WR_chan_1,
+ output reg [15:0] tx_data_bus) ;
+
+ // States
+ `define IDLE 3'd0
+ `define WAIT 3'd1
+ `define READ_TARGET 3'd2
+ `define READ_LENGTH 3'd3
+ `define FORWARD_DATA 3'd4
+ `define SKIP_REST 3'd5
+
+ `define TXCHAN0 5'h0
+ `define TXCHAN1 5'h1
+ `define TXCMD 5'h1F
+
+ reg [2:0] reader_state;
+ reg [2:0] reader_next_state;
+ reg [4:0] channel;
+ reg [8:0] pkt_length;
+ reg [8:0] read_length;
+
+ // Fifo's flags
+ wire [15:0] fifodata ;
+ reg rdreq;
+ reg skip;
+ wire pkt_waiting;
+
+ // FIFO
+ usb_packet_fifo tx_usb_fifo
+ ( .reset(reset),
+ .clock_in(usb_clock),
+ .clock_out(tx_clock),
+ .ram_data_in(usb_data),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .skip_packet(skip)
+ );
+
+ // FSM
+ always @(posedge tx_clock)
+ begin
+ if (reset)
+ begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ WR_chan_0 <= 0;
+ WR_chan_1 <= 0;
+ WR_cmd <= 0;
+ end
+ else
+ begin
+ reader_state = reader_next_state;
+ case(reader_state)
+ `IDLE:
+ begin
+ reader_next_state <= pkt_waiting ? `WAIT : `IDLE;
+ rdreq <= pkt_waiting;
+
+ // Unset the done flag from the previous
packet
+ cmd_done <= 0;
+ chan_1_done <= 0;
+ chan_0_done <= 0;
+ end
+
+ // Wait for the fifo's data
+ `WAIT:
+ begin
+ reader_next_state <= `READ_TARGET;
+ end
+
+ `READ_TARGET:
+ begin
+ reader_next_state <= `READ_LENGTH;
+
+ // Unset the done flag from the previous
packet
+ cmd_done <= 0;
+ chan_1_done <= 0;
+ chan_0_done <= 0;
+
+ channel = (fifodata & 16'h1F);
+
+ // Forward data
+ tx_data_bus <= fifodata;
+ case (channel)
+ `TXCHAN0: WR_chan_0 <= 1;
+ `TXCHAN1: WR_chan_1 <= 1;
+ `TXCMD: WR_cmd <= 1;
+ //invalid channel -> channel 0;
+ default: WR_chan_0 <= 1;
+ endcase
+ end
+
+ `READ_LENGTH:
+ begin
+ reader_next_state <= `FORWARD_DATA;
+
+ // Plus two bytes for timestamp
+ pkt_length <= (fifodata & 16'h1FF) + 2;
+ read_length <= 9'd0;
+
+ // Forward data
+ tx_data_bus <= fifodata;
+ end
+
+ `FORWARD_DATA:
+ begin
+ read_length <= read_length + 2;
+
+ // If end of payload...
+ if (read_length == pkt_length)
+ begin
+ reader_next_state <= `SKIP_REST;
+ // If the packet is 512 bytes, don't skip
+ skip <= pkt_length < 506;
+ end
+ else if (read_length == pkt_length - 2)
+ rdreq <= 0;
+
+ // Forward data
+ tx_data_bus <= fifodata;
+ end
+
+ `SKIP_REST:
+ begin
+ reader_next_state <= pkt_waiting ? `READ_TARGET : `IDLE;
+
+ // Data pushing done
+ WR_chan_0 <= 0;
+ WR_chan_1 <= 0;
+ WR_cmd <= 0;
+
+ case (channel)
+ `TXCHAN0: chan_0_done <= 1;
+ `TXCHAN1: chan_0_done <= 1;
+ `TXCMD: cmd_done <= 1;
+ //invalid channel -> channel 0;
+ default: WR_chan_0 <= 1;
+ endcase
+
+ rdreq <= pkt_waiting;
+ skip <= 0;
+ end
+ // reset
+ default:
+ begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ end
+ endcase
+ end
+ end
+
+endmodule
+
+
+
\ No newline at end of file
Copied:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo.v
(from rev 5051,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_packet_fifo.v)
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo.v
2007-04-21 17:15:14 UTC (rev 5062)
@@ -0,0 +1,90 @@
+module usb_packet_fifo
+ ( input reset,
+ input clock_in,
+ input clock_out,
+ input [15:0]ram_data_in,
+ input write_enable,
+ output reg [15:0]ram_data_out,
+ output reg pkt_waiting,
+ input read_enable,
+ input skip_packet ) ;
+
+ /* Some parameters for usage later on */
+ parameter DATA_WIDTH = 16 ;
+ parameter NUM_PACKETS = 4 ;
+
+ /* Create the RAM here */
+ reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
+
+ /* Create the address signals */
+ reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
+ reg [7:0] usb_ram_offset ;
+ reg [1:0] usb_ram_packet ;
+
+ wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
+
+ assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
+
+ // Check if there is one full packet to process
+ always @(usb_ram_ain, usb_ram_aout)
+ begin
+ if (reset)
+ pkt_waiting <= 0;
+ else if (usb_ram_ain >= usb_ram_aout)
+ pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
+ else
+ pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >=
256;
+ end
+
+ /* RAM Write Address process */
+ always @(posedge clock_in)
+ begin
+ if( reset )
+ usb_ram_ain <= 0 ;
+ else
+ if( write_enable )
+ begin
+ usb_ram_ain <= usb_ram_ain + 1 ;
+ end
+ end
+
+ /* RAM Writing process */
+ always @(posedge clock_in)
+ begin
+ if( write_enable )
+ begin
+ usb_ram[usb_ram_ain] <= ram_data_in ;
+ end
+ end
+
+ /* RAM Read Address process */
+ always @(posedge clock_out)
+ begin
+ if( reset )
+ begin
+ usb_ram_packet <= 0 ;
+ usb_ram_offset <= 0 ;
+ end
+ else
+ if( skip_packet )
+ begin
+ usb_ram_packet <= usb_ram_packet + 1 ;
+ usb_ram_offset <= 0 ;
+ end
+ else if(read_enable)
+ if( usb_ram_offset == 8'b11111111 )
+ begin
+ usb_ram_offset <= 0 ;
+ usb_ram_packet <= usb_ram_packet + 1 ;
+ end
+ else
+ usb_ram_offset <= usb_ram_offset + 1 ;
+ end
+
+ /* RAM Reading Process */
+ always @(posedge clock_out)
+ begin
+ ram_data_out <= usb_ram[usb_ram_aout] ;
+ end
+
+endmodule
\ No newline at end of file
Deleted:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
Deleted:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
Deleted:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-21
17:03:27 UTC (rev 5061)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-21
17:15:14 UTC (rev 5062)
@@ -244,24 +244,24 @@
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 9
-Project_File_0 = ./usb_packet_fifo_test.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487761 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_1 = ./tx_buffer_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177096513 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = ../inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177095630 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = ../inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177096700 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = ../inband/usrp/fpga/sdr_lib/data_packet_fifo.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_5 = ../inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487356 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_6 = ./chan_fifo_readers_test.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177095370 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_7 = ./usb_fifo_reader_test.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177093134 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = ../inband/usrp/fpga/sdr_lib/tx_buffer.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177096284 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_0 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174960 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174930 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = ./usb_packet_fifo_test.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487761 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174948 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = ./tx_buffer_test.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174598 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_6 = ../inband/usrp/fpga/inband_lib/tx_buffer.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174685 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = ./chan_fifo_readers_test.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174246 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = ./usb_fifo_reader_test.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177093134 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -291,6 +291,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1}
{Z:/wc/simulations/chan_fifo_readers_test.v 0 0}
{Z:/wc/simulations/tx_buffer_test.v 0 1}
{Z:/wc/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/data_packet_fifo.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v 0 0}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified: gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-04-21 17:03:27 UTC (rev 5061)
+++ gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-04-21 17:15:14 UTC (rev 5062)
@@ -1,5 +1,6 @@
module tx_buffer_test();
+// Inputs
reg usbclk;
reg bus_reset;
reg reset;
@@ -10,6 +11,7 @@
reg txstrobe;
reg clear_status;
+// Outputs
wire have_space;
wire tx_underrun;
wire [15:0] tx_i_0;
@@ -23,16 +25,87 @@
wire tx_empty;
wire [11:0] debugbus;
+// Tests
+reg [15:0] i ;
+
tx_buffer tx_buffer_test (
.usbclk(usbclk),
.reset(reset),
.usbdata(usbdata),
.WR(WR),
.txclk(txclk),
+ .txstrobe(txstrobe),
+ .tx_empty(tx_empty),
+ .have_space(have_space),
+ .tx_underrun(tx_underrun),
.tx_i_0(tx_i_0),
.tx_i_1(tx_i_1),
+ .tx_i_2(tx_i_2),
+ .tx_i_3(tx_i_3),
.tx_q_0(tx_q_0),
- .tx_q_1(tx_q_1)
+ .tx_q_1(tx_q_1),
+ .tx_q_2(tx_q_2),
+ .tx_q_3(tx_q_3),
+ .debugbus(debug_bus)
);
+// Initialize Inputs
+ initial begin
+ // Setup the initial conditions
+ reset = 1;
+ usbclk = 0;
+ usbdata = 0;
+ WR = 0;
+ txclk = 0;
+ i = 0 ;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge usbclk)
+ reset = 1'b0 ;
+ end
+
+ // Write one half full packet (channel 0)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 1)
+ // payload size
+ usbdata = 32;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+
+ i = 0;
+
+ // Write one full packet (channel 1)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 0)
+ // channel
+ usbdata = 1;
+ else if (i == 1)
+ // payload size
+ usbdata = 504;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ end
+
+
+always
+ #3 txclk = ~txclk ;
+
+always
+ #3 txstrobe = ~txstrobe ;
+
+always
+ #5 usbclk = ~usbclk ;
+
endmodule
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- [Commit-gnuradio] r5062 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga inband/usrp/fpga/inband_lib inband/usrp/fpga/sdr_lib simulations,
thottelt <=