[Commit-gnuradio] r5104 - gnuradio/branches/developers/matt/u2f/top/u2_sim_top

[matt]

Author: matt
Date: 2007-04-25 02:02:13 -0600 (Wed, 25 Apr 2007)
New Revision: 5104

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_sim_top/u2_sim_top.v
Log:
updated to new port names


Modified: gnuradio/branches/developers/matt/u2f/top/u2_sim_top/u2_sim_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim_top/u2_sim_top.v   
2007-04-25 08:01:44 UTC (rev 5103)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim_top/u2_sim_top.v   
2007-04-25 08:02:13 UTC (rev 5104)
@@ -74,10 +74,6 @@
    wire        ser_rkmsb;
    
    // CPLD interface
-   wire        spi_cpld_en;
-   wire        spi_cpld_dout;
-   wire        spi_cpld_din;
-   wire        spi_cpld_clk;   // temporary bootstrap clock
    
    // ADC
    wire [13:0] adc_a;
@@ -180,6 +176,13 @@
                     .debug             (debug[31:0]),
                     .debug_clk         (debug_clk[1:0]),
                     .exp_pps_out       (exp_pps_out),
+                    .ser_enable        (ser_enable),
+                    .ser_prbsen        (ser_prbsen),
+                    .ser_loopen        (ser_loopen),
+                    .ser_rx_en         (ser_rx_en),
+                    .cpld_start        (cpld_start),
+                    .cpld_mode         (cpld_mode),
+                    .cpld_done         (cpld_done),
                     .adc_oen_a         (adc_oen_a),
                     .adc_pdn_a         (adc_pdn_a),
                     .adc_oen_b         (adc_oen_b),
@@ -194,8 +197,13 @@
                     .clk_sel           (clk_sel[1:0]),
                     .sclk              (sclk),
                     .sen_clk           (sen_clk),
+                    .sen_dac           (sen_dac),
                     .sdi               (sdi),
                     // Inputs
+                    .clk_fpga          (clk_fpga),
+                    .aux_clk           (aux_clk),
+                    .clk_to_mac        (clk_to_mac),
+                    .pps_in            (pps_in),
                     .exp_pps_in        (exp_pps_in),
                     .GMII_COL          (GMII_COL),
                     .GMII_CRS          (GMII_CRS),
@@ -213,32 +221,17 @@
                     .PHY_INTn          (PHY_INTn),
                     .PHY_RESETn        (PHY_RESETn),
                     .PHY_CLK           (PHY_CLK),
-                    .RAM_D             (RAM_D[17:0]),
-                    .RAM_A             (RAM_A[18:0]),
-                    .RAM_CE1n          (RAM_CE1n),
-                    .RAM_CENn          (RAM_CENn),
-                    .RAM_CLK           (RAM_CLK),
-                    .RAM_WEn           (RAM_WEn),
-                    .RAM_OEn           (RAM_OEn),
-                    .RAM_LDn           (RAM_LDn),
-                    .ser_enable        (ser_enable),
-                    .ser_prbsen        (ser_prbsen),
-                    .ser_loopen        (ser_loopen),
                     .ser_tx_clk        (ser_tx_clk),
                     .ser_t             (ser_t[15:0]),
                     .ser_tklsb         (ser_tklsb),
                     .ser_tkmsb         (ser_tkmsb),
                     .ser_rx_clk        (ser_rx_clk),
-                    .ser_rx_en         (ser_rx_en),
                     .ser_r             (ser_r[15:0]),
                     .ser_rklsb         (ser_rklsb),
                     .ser_rkmsb         (ser_rkmsb),
-                    .spi_cpld_en       (spi_cpld_en),
-                    .spi_cpld_dout     (spi_cpld_dout),
-                    //.spi_cpld_din    (spi_cpld_din),
-                    //.spi_cpld_clk    (spi_cpld_clk),
-                    .POR               (POR),             // FIXME
-                    .aux_clk           (aux_clk),         // FIXME
+                    .cpld_din          (cpld_din),
+                    .cpld_clk          (cpld_clk),
+                    .cpld_detached     (cpld_detached),
                     .adc_a             (adc_a[13:0]),
                     .adc_ovf_a         (adc_ovf_a),
                     .adc_b             (adc_b[13:0]),
@@ -247,10 +240,6 @@
                     .sda_pad_i         (sda_pad_i),
                     .clk_func          (clk_func),
                     .clk_status        (clk_status),
-                    .clk_fpga          (clk_fpga),
-                    .clk_to_mac        (clk_to_mac),
-                    .pps_in            (pps_in),
-                    .sen_dac           (sen_dac),
                     .sdo               (sdo),
                     .sen_tx_db         (sen_tx_db),
                     .sclk_tx_db        (sclk_tx_db),
@@ -281,6 +270,6 @@
 
 // Local Variables:
 // verilog-library-directories:("." "subdir" "subdir2")
-// 
verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v")
 // verilog-library-extensions:(".v" ".h")
 // End: