[Commit-gnuradio] r5105 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-04-25 02:05:19 -0600 (Wed, 25 Apr 2007)
New Revision: 5105

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
added processor and ram, fixed some ignores



Property changes on: gnuradio/branches/developers/matt/u2f/top/u2_basic
___________________________________________________________________
Name: svn:ignore
   - xst
_ngo
_xmsgs
*.stx
*.tspec
*.xml
*.gyd
*.ngr
*.tim
*.err
*.lso
*.bld
*.cmd_log
*.ise_ISE_Backup
*.mfd
*.vm6
*.syr
*.xst
*.csv
*.html
*.jed
*.pad
*.ng*
*.pnx
*.rpt
*.prj
*_html
*_log
*.lfp
*.bit
*.bin
*.vcd
*.unroutes
*.drc
*_map.*
*_guide.*
*.twr
*.twx
a.out

   + xst
_ngo
_xmsgs
*.stx
*.tspec
*.xml
*.gyd
*.ngr
*.tim
*.err
*.lso
*.bld
*.cmd_log
*.ise_ISE_Backup
*.mfd
*.vm6
*.syr
*.xst
*.csv
*.html
*.jed
*.pad
*.ng*
*.pnx
*.rpt
*.prj
*_html
*_log
*.lfp
*.bit
*.bin
*.vcd
*.unroutes
*.drc
*_map.*
*_guide.*
*.twr
*.twx
a.out
*.xpi
*_pad.txt
*.bgn
*.par


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-04-25 08:02:13 UTC (rev 5104)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-04-25 08:05:19 UTC (rev 5105)
@@ -12,6 +12,12 @@
 
 module u2_basic
   (
+   // Clocks
+   input clk_fpga,
+   input aux_clk,
+   input clk_to_mac,
+   input pps_in,
+   
    // Misc, debug
    output led1,
    output led2,
@@ -47,16 +53,6 @@
    input PHY_RESETn,
    input PHY_CLK,   // possibly use on-board osc
 
-   // RAM
-   input [17:0] RAM_D,
-   input [18:0] RAM_A,
-   input RAM_CE1n,
-   input RAM_CENn,
-   input RAM_CLK,
-   input RAM_WEn,
-   input RAM_OEn,
-   input RAM_LDn,
-   
    // SERDES
    output ser_enable,
    output ser_prbsen,
@@ -74,12 +70,12 @@
    input ser_rkmsb,
    
    // CPLD interface
-   input spi_cpld_en,
-   input spi_cpld_dout,
-   input POR,
-   //input spi_cpld_din,
-   input aux_clk,   // temporary bootstrap clock
-   //input spi_cpld_clk,   // temporary bootstrap clock
+   output cpld_start,
+   output cpld_mode,
+   output cpld_done,
+   input cpld_din,
+   input cpld_clk,
+   input cpld_detached,
    
    // ADC
    input [13:0] adc_a,
@@ -110,11 +106,6 @@
    input clk_func,        // FIXME is an input to control the 9510
    input clk_status,
 
-   // Clocks
-   input clk_fpga,
-   input clk_to_mac,
-   input pps_in,
-   
    // Generic SPI
    output sclk,
    output sen_clk,
@@ -137,7 +128,7 @@
    input sclk_tx_dac,
    input sdi_tx_dac,
 
-   input [15:0] io_tx,
+   inout [15:0] io_tx,
 
    // RX DBoard
    input sen_rx_db,
@@ -154,11 +145,11 @@
    input sclk_rx_dac,
    input sdi_rx_dac,
    
-   input [15:0] io_rx
+   inout [15:0] io_rx
    );
    
    wire        dsp_clk, wb_clk, wb_rst, reset;
-   
+
    assign      debug = {clk_status, reset, sen_clk, sclk, sdi, sdo};
    assign      debug_clk[0] = aux_clk;
    assign      debug_clk[1] = clk_fpga;        
@@ -168,12 +159,11 @@
    //   1   Main Processor (aeMB)
 
    //  Address bus is 16 bits.  Top 4 addr bits select the slave
-   //  11+ Slaves
-   //   0   Output control lines
+   //   0   System RAM
    //   1   General SPI
    //   2   I2C
    //   3   GPIOs for TX and RX DB
-   //   4   SPI - MDC for ethernet
+   //   4   Output control lines
    //   5   SPI - TXDB
    //   6   SPI - TXDAC
    //   7   SPI - TXADC
@@ -182,39 +172,90 @@
    //   10  SPI - TXADC
    //   11  Interrupt controller?
    
-`define dw 32
-`define aw 16
-`define sw 4
 
-   wire [`dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
-   wire [`dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, 
s2_dat_i, s3_dat_i,
-                 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, 
s6_dat_i, s7_dat_i;
-   wire [`aw-1:0] m0_adr, m1_adr, 
s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
-   wire [`sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, 
s5_sel, s6_sel, s7_sel;
-   wire          m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, 
s5_ack, s6_ack, s7_ack;
-   wire          m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, 
s5_stb, s6_stb, s7_stb;
-   wire          m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, 
s5_cyc, s6_cyc, s7_cyc;
-   wire          m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, 
s5_err, s6_err, s7_err;
-   wire          m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, 
s5_rty, s6_rty, s7_rty;
-   wire          m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, 
s6_we, s7_we;
-   wire          m0_cab, m1_cab, s0_cab, s1_cab, s2_cab, s3_cab, s4_cab, 
s5_cab, s6_cab, s7_cab;
+   parameter   dw = 32;  // Data bus width
+   parameter   aw = 16;  // Address bus width, for byte addressibility, 16 = 
64K byte memory space
+   parameter   sw = 4;   // Select width -- 32-bit data bus with 8-bit 
granularity.  
+   // FIXME Does this mean we ignore the bottom 2 address bits? or should they 
not be there?
    
-   // Output control lines, organized in 4 8-bit segments -- clock, serdes, 
adc, led+misc
-   wire [7:0]    clock_outs, serdes_outs, adc_outs, misc_outs;
+   // Wishbone signals
+   wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, 
s2_dat_i, s3_dat_i,
+                s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, 
s6_dat_i, s7_dat_i;
+   wire [aw-1:0] m0_adr, m1_adr, 
s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+   wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, 
s5_sel, s6_sel, s7_sel;
+   wire         m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, 
s5_ack, s6_ack, s7_ack;
+   wire         m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, 
s5_stb, s6_stb, s7_stb;
+   wire         m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, 
s5_cyc, s6_cyc, s7_cyc;
+   wire         m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, 
s5_err, s6_err, s7_err;
+   wire         m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, 
s5_rty, s6_rty, s7_rty;
+   wire         m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, 
s7_we;
+   wire         m0_cab, m1_cab, s0_cab, s1_cab, s2_cab, s3_cab, s4_cab, 
s5_cab, s6_cab, s7_cab;
    
-   assign        {clk_en[1:0], clk_sel[1:0]} = clock_outs[3:0];  //= { 4'b0, 
clk_en[1:0], clk_sel[1:0] };
-   assign        {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = 
serdes_outs[3:0]; // = { 4'b0, ser_enable, ser_prbsen, ser_loopen, ser_rx_en };
-   assign        { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = 
adc_outs[3:0]; // = { 4'b0, adc_oe_a_n, adc_pdn_a, adc_oe_b_n, adc_pdn_b };
-   assign        {led2, led1} = misc_outs[1:0]; // = { 6'b0, led2, led1 };
+   // 
////////////////////////////////////////////////////////////////////////////////////
+   // Output control lines, SLAVE #4
+   //       organized in 4 8-bit segments -- clock, serdes, adc, led+misc
    
-   wb_output_pins32 control_lines
-     
(.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s0_dat_o),.wb_dat_o(s0_dat_i),
-      
.wb_we_i(s0_we),.wb_sel_i(s0_sel),.wb_stb_i(s0_stb),.wb_ack_o(s0_ack),.wb_cyc_i(s0_cyc),
-      .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} )  );
+   // 
/////////////////////////////////////////////////////////////////////////////////////////
+   // Bootstrap RAM
+   reg [7:0]    ram [0:4095];
+   wire [11:0]          ram_addr_w, ram_addr_r;
+   wire [7:0]   ram_data_w;
+   reg [7:0]    ram_data_r;
+   
+   ram_loader ram_loader (.clk_i(aux_clk),.reset_i(reset),
+                         // CPLD Interface
+                         .cfg_clk_i(cpld_clk),
+                         .cfg_data_i(cpld_din),
+                         .start_o(cpld_start),
+                         .mode_o(cpld_mode),
+                         .done_o(cpld_done),
+                         .detached_i(detached),
+                         // Asynchronous RAM Interface
+                         .ram_addr(ram_addr_w),
+                         .ram_data(ram_data_w),
+                         .ram_we(ram_we) );
+   
+   always @(posedge aux_clk)
+     if(ram_we)
+       ram[ram_addr_w] <= #1 ram_data_w;
+   
+   always @(posedge aux_clk)
+     ram_data_r <= #1 ram[ram_addr_r];
 
-   wire [15:0]         rom_addr;
-   wire [47:0]         rom_data;
+   wire [15:0]          counter;
    
+   assign       ram_addr_r = counter[15:4];
+   
+   wire [15:0]          rom_addr;
+   wire [47:0]          rom_data;
+   
+   // 
//////////////////////////////////////////////////////////////////////////////////////////
+   // Master # 1 -- Internal processor
+
+   wire         iwb_stb, iwb_ack, bus_error, proc_int;
+   wire [aw-1:0] iwb_adr;
+   wire [dw-1:0] iwb_dat;
+       
+   aeMB_core #(.ISIZ(16),.DSIZ(32))
+     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+          // Instruction Wishbone bus to I-RAM
+          .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
+          .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+          // Data Wishbone bus to system bus fabric
+          
.dwb_we_o(m1_we),.dwb_stb_o(m1_stb),.dwb_dat_o(m1_dat_i),.dwb_adr_o(m1_adr),
+          .dwb_dat_i(m1_dat_o),.dwb_ack_i(m1_ack),
+          // Interrupts and exceptions
+          .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+
+   assign       m1_cab = 1'b0;
+   assign       m1_sel = 4'b1111;  // Until core can do byte-addressing
+   assign       m1_cyc = m1_stb;   // Until core properly drives this
+   assign       bus_error = m1_err | m1_rty;
+   assign       proc_int = 1'b0;
+   
+   
////////////////////////////////////////////////////////////////////////////////////////
+   // Clock bootstrapping
    clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data));
    
    wb_bus_writer bus_writer(.rom_addr  (rom_addr),
@@ -230,39 +271,92 @@
                            .wb_clk_i   (wb_clk),
                            .wb_rst_i   (wb_rst),
                            .wb_ack_i   (m0_ack));
+   assign       m0_cab = 1'b0;
 
+   
//////////////////////////////////////////////////////////////////////////////////////////
+   // Master # 0 -- System Controller, handles reset and clocks
    system_control sysctrl (.aux_clk(aux_clk),.clk_fpga(clk_fpga),.POR(POR),
                           .dsp_clk(dsp_clk),.reset_out(reset),
                           .wb_clk_o(wb_clk),.wb_rst_o(wb_rst),.wb_rst_o_alt(),
                           .start(start),.done(done) );
-      
+
+   // 
/////////////////////////////////////////////////////////////////////////////////////////
+   // Dual Ported RAM -- Slave #0
+   // I-port connects directly to processor, D-port connects to bus (slave 0)
+   
+   ram_wb_harvard #(.AWIDTH(12))
+     ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+            
.iwb_adr_i(iwb_adr),.iwb_dat_o(iwb_dat),.iwb_stb_i(iwb_stb),.iwb_ack_o(iwb_ack),
+            .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
+            .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb));
+   
+   // SPI -- Slave #1
    spi_top shared_spi
      
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),.wb_dat_o(s1_dat_i),
       
.wb_sel_i(s1_sel),.wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_cyc_i(s1_cyc),.wb_ack_o(s1_ack),
       .wb_err_o(s1_err),.wb_int_o(s1_int),
-      
.ss_pad_o({sen_dac,sen_clk}),.sclk_pad_o(sclk),.mosi_pad_o(),.miso_pad_i() );
+      
.ss_pad_o({sen_dac,sen_clk}),.sclk_pad_o(sclk),.mosi_pad_o(sdi),.miso_pad_i(sdo)
 );
 
-   i2c_master_top i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(), 
-                      
.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
-                      .wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),
-                      .wb_ack_o(s2_ack),.wb_inta_o(st_int),
-                      
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
-                      
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+   // I2C -- Slave #2
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+         .wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
+         .wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),
+         .wb_ack_o(s2_ack),.wb_inta_o(st_int),
+         
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+         
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+   
+   // GPIOs -- Slave #3
+   wire         s3_ack_a, s3_ack_b, s3_ack_c, s3_ack_d;
+   assign       s3_ack = s3_ack_a | s3_ack_b | s3_ack_c | s3_ack_d;
 
-   assign      m1_cyc=1'b0;
+   simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(wb_rst),
+                     
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[0]),.adr_i(s3_adr),.we_i(s3_we),
+                     
.dat_i(s3_dat_o[7:0]),.dat_o(s3_dat_i[7:0]),.ack_o(s3_ack_a),
+                     .gpio(io_tx[7:0]) );
    
+   simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(wb_rst),
+                     
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[1]),.adr_i(s3_adr),.we_i(s3_we),
+                     
.dat_i(s3_dat_o[15:8]),.dat_o(s3_dat_i[15:8]),.ack_o(s3_ack_b),
+                     .gpio(io_tx[15:8]) );
+   
+   simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(wb_rst),
+                     
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[2]),.adr_i(s3_adr),.we_i(s3_we),
+                     
.dat_i(s3_dat_o[23:16]),.dat_o(s3_dat_i[23:16]),.ack_o(s3_ack_c),
+                     .gpio(io_rx[7:0]) );
+   
+   simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(wb_rst),
+                     
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[3]),.adr_i(s3_adr),.we_i(s3_we),
+                     
.dat_i(s3_dat_o[31:24]),.dat_o(s3_dat_i[31:24]),.ack_o(s3_ack_d),
+                     .gpio(io_rx[15:8]) );
+   
+   //  Basic Outputs -- Slave #4
+   wire [7:0]   clock_outs, serdes_outs, adc_outs, misc_outs;
+   assign       {clk_en[1:0], clk_sel[1:0]} = clock_outs[3:0];  //= { 4'b0, 
clk_en[1:0], clk_sel[1:0] };
+   assign       {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = 
serdes_outs[3:0]; // = { 4'b0, ser_enable, ser_prbsen, ser_loopen, ser_rx_en };
+   assign       { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = 
adc_outs[3:0]; // = { 4'b0, adc_oe_a_n, adc_pdn_a, adc_oe_b_n, adc_pdn_b };
+   assign       {led2, led1} = misc_outs[1:0]; // = { 6'b0, led2, led1 };
+   
+   wb_output_pins32 control_lines
+     
(.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s4_dat_o),.wb_dat_o(s4_dat_i),
+      
.wb_we_i(s4_we),.wb_sel_i(s4_sel),.wb_stb_i(s4_stb),.wb_ack_o(s4_ack),.wb_cyc_i(s4_cyc),
+      .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} )  );
+   
+   
//////////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Shared Bus
    wb_conbus_top #(.s0_addr_w(4),.s0_addr(4'h0),.s1_addr_w(4),.s1_addr(4'h1),
                   .s27_addr_w(4),.s2_addr(4'h2),.s3_addr(4'h3),.s4_addr(4'h4),
                   .s5_addr(4'h5),.s6_addr(4'h6),.s7_addr(4'h7),
-                  .dw(`dw),.aw(`aw),.sw(`sw)) wb_conbus_top
+                  .dw(dw),.aw(aw),.sw(sw)) wb_conbus_top
      (.clk_i(wb_clk),.rst_i(wb_rst),
       
       
.m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
       
.m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),.m0_cab_i(m0_cab),
       
.m1_dat_o(m1_dat_o),.m1_ack_o(m1_ack),.m1_err_o(m1_err),.m1_rty_o(m1_rty),.m1_dat_i(m1_dat_i),
       
.m1_adr_i(m1_adr),.m1_sel_i(m1_sel),.m1_we_i(m1_we),.m1_cyc_i(m1_cyc),.m1_stb_i(m1_stb),.m1_cab_i(m1_cab),
-
+      
       
.m2_cyc_i(1'b0),.m3_cyc_i(1'b0),.m4_cyc_i(1'b0),.m5_cyc_i(1'b0),.m6_cyc_i(1'b0),.m7_cyc_i(1'b0),
+      
.m2_stb_i(1'b0),.m3_stb_i(1'b0),.m4_stb_i(1'b0),.m5_stb_i(1'b0),.m6_stb_i(1'b0),.m7_stb_i(1'b0),
       .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o 
(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
       
.s0_cab_o(s0_cab),.s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
       .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o 
(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
@@ -281,11 +375,18 @@
       
.s7_cab_o(s7_cab),.s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
       );
       
-   assign      s3_ack = 1'b0;
-   assign      s4_ack = 1'b0;
-   assign      s5_ack = 1'b0;
-   assign      s6_ack = 1'b0;
-   assign      s7_ack = 1'b0;
+   assign       s5_ack = 1'b0; 
+   assign       s5_err = 1'b0;
+   assign       s5_rty = 1'b0;
+   assign       s5_dat_i = 32'd0;
+   assign       s6_ack = 1'b0; 
+   assign       s6_err = 1'b0;
+   assign       s6_rty = 1'b0;
+   assign       s6_dat_i = 32'd0;
+   assign       s7_ack = 1'b0; 
+   assign       s7_err = 1'b0;
+   assign       s7_rty = 1'b0;
+   assign       s7_dat_i = 32'd0;
    
 endmodule // u2_basic