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[Commit-gnuradio] r5112 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5112 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells simulations |
|
Date: |
Wed, 25 Apr 2007 15:17:46 -0600 (MDT) |
Author: thottelt
Date: 2007-04-25 15:17:46 -0600 (Wed, 25 Apr 2007)
New Revision: 5112
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
Modified:
gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
new fifo
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-25 21:17:46 UTC (rev 5112)
@@ -0,0 +1,99 @@
+`default_nettype none
+
+module usb_packet_fifo2(reset, usb_clock, fpga_clock, write_enable,
write_data,
+ read_enable, skip_packet, read_data, have_space, pkt_waiting) ;
+
+ /* Module parameters */
+ parameter LOG2_N = 2 ;
+ parameter WIDTH = 16 ;
+
+ input wire reset;
+ input wire usb_clock ;
+ input wire fpga_clock ;
+ input wire write_enable ;
+ input wire [WIDTH-1:0] write_data ;
+ input wire read_enable ;
+ input wire skip_packet ;
+ output wire [WIDTH-1:0] read_data ;
+ output wire have_space ;
+ output wire pkt_waiting ;
+
+
+ /* Variable for generate statement */
+ genvar i ;
+
+ /* Local wires for FIFO connections */
+ reg fifo_resets[2**LOG2_N-1:0] ;
+ reg fifo_we[2**LOG2_N-1:0] ;
+ wire fifo_re[2**LOG2_N-1:0] ;
+ wire fifo_wdata[2**LOG2_N-1:0] ;
+ wire fifo_rdata[2**LOG2_N-1:0] ;
+ wire fifo_rempty[2**LOG2_N-1:0] ;
+ wire fifo_rfull[2**LOG2_N-1:0] ;
+ wire fifo_wempty[2**LOG2_N-1:0] ;
+ wire fifo_wfull[2**LOG2_N-1:0] ;
+
+ /* FIFO Select for read and write ports */
+ reg [LOG2_N-1:0] fifo_rselect ;
+ reg [LOG2_N-1:0] fifo_wselect ;
+
+ /* Assign have_space to empty flag of currently selected write FIFO */
+ assign have_space = fifo_wempty[fifo_wselect] ;
+
+ /* Assign pkt_waiting to full flag of currently selected read FIFO */
+ assign pkt_waiting = fifo_rfull[fifo_rselect] ;
+
+ /* Assign the read_data to the output of the currently selected FIFO */
+ assign read_data = fifo_rdata[fifo_rselect] ;
+
+ /* Increment fifo_rselect here */
+ always @(posedge fpga_clock)
+ begin
+ if (fifo_rempty[fifo_rselect])
+ fifo_rselect <= fifo_rselect + 1 ;
+ end
+
+ /* Increment fifo_wselect here */
+ always @(posedge usb_clock)
+ begin
+ if (fifo_wfull[fifo_wselect])
+ fifo_wselect <= fifo_wselect + 1 ;
+ end
+
+ /* Route skip_packet to the correct fifo_resets signal based on the
fifo_rselect */
+ always @(posedge fpga_clock)
+ begin
+ if (skip_packet)
+ begin
+ fifo_resets[fifo_rselect] <= 1 ;
+ fifo_rselect <= fifo_rselect + 1 ;
+ end
+ else
+ fifo_resets[fifo_rselect] <= 0;
+ end
+
+ /* Route write_enable to the correct fifo_we signal based on the
fifo_wselect */
+ always @(posedge usb_clock)
+ begin
+ fifo_we[fifo_wselect] <= write_enable;
+ end
+
+ /* Generate all the single packet FIFOs */
+ generate
+ for( i = 0 ; i < 2**LOG2_N ; i = i + 1 )
+ begin : generate_single_packet_fifos
+ assign fifo_wdata[i] = write_data ;
+ fifo_512 single_packet_fifo(.wrclk ( usb_clock ),
+ .rdlck ( fpga_clock ),
+ .aclr ( fifo_resets[i] ),
+ .wrreq ( fifo_we[i] ),
+ .data ( fifo_wdata[i] ),
+ .rdreq ( fifo_re[i] ),
+ .q ( fifo_rdata[i] ),
+ .rdfull ( fifo_rfull[i] ),
+ .rdempty( fifo_rempty[i] ),
+ .wrfull ( fifo_wfull[i] ),
+ .wrempty( fifo_wempty[i] ) ) ;
+ end
+ endgenerate
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
2007-04-25 21:17:46 UTC (rev 5112)
@@ -0,0 +1,116 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2006 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+ (rect 0 0 160 184)
+ (text "fifo_512" (rect 58 1 109 17)(font "Arial" (font_size 10)))
+ (text "inst" (rect 8 168 25 180)(font "Arial" ))
+ (port
+ (pt 0 32)
+ (input)
+ (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
+ (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
+ (line (pt 0 32)(pt 16 32)(line_width 3))
+ )
+ (port
+ (pt 0 56)
+ (input)
+ (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+ (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+ (line (pt 0 56)(pt 16 56)(line_width 1))
+ )
+ (port
+ (pt 0 72)
+ (input)
+ (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+ (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+ (line (pt 0 72)(pt 16 72)(line_width 1))
+ )
+ (port
+ (pt 0 104)
+ (input)
+ (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+ (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+ (line (pt 0 104)(pt 16 104)(line_width 1))
+ )
+ (port
+ (pt 0 120)
+ (input)
+ (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+ (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+ (line (pt 0 120)(pt 16 120)(line_width 1))
+ )
+ (port
+ (pt 0 160)
+ (input)
+ (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+ (text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8)))
+ (line (pt 0 160)(pt 16 160)(line_width 1))
+ )
+ (port
+ (pt 160 40)
+ (output)
+ (text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+ (text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))
+ (line (pt 160 40)(pt 144 40)(line_width 1))
+ )
+ (port
+ (pt 160 56)
+ (output)
+ (text "wrempty" (rect 0 0 50 14)(font "Arial" (font_size 8)))
+ (text "wrempty" (rect 98 50 137 63)(font "Arial" (font_size 8)))
+ (line (pt 160 56)(pt 144 56)(line_width 1))
+ )
+ (port
+ (pt 160 96)
+ (output)
+ (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+ (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
+ (line (pt 160 96)(pt 144 96)(line_width 3))
+ )
+ (port
+ (pt 160 120)
+ (output)
+ (text "rdfull" (rect 0 0 28 14)(font "Arial" (font_size 8)))
+ (text "rdfull" (rect 117 114 141 127)(font "Arial" (font_size
8)))
+ (line (pt 160 120)(pt 144 120)(line_width 1))
+ )
+ (port
+ (pt 160 136)
+ (output)
+ (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
+ (text "rdempty" (rect 102 130 140 143)(font "Arial" (font_size
8)))
+ (line (pt 160 136)(pt 144 136)(line_width 1))
+ )
+ (drawing
+ (text "16 bits x 256 words" (rect 63 156 144 168)(font "Arial"
))
+ (line (pt 16 16)(pt 144 16)(line_width 1))
+ (line (pt 144 16)(pt 144 168)(line_width 1))
+ (line (pt 144 168)(pt 16 168)(line_width 1))
+ (line (pt 16 168)(pt 16 16)(line_width 1))
+ (line (pt 16 84)(pt 144 84)(line_width 1))
+ (line (pt 16 148)(pt 144 148)(line_width 1))
+ (line (pt 16 66)(pt 22 72)(line_width 1))
+ (line (pt 22 72)(pt 16 78)(line_width 1))
+ (line (pt 16 114)(pt 22 120)(line_width 1))
+ (line (pt 22 120)(pt 16 126)(line_width 1))
+ )
+)
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
2007-04-25 21:17:46 UTC (rev 5112)
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component fifo_512
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdfull : OUT STD_LOGIC ;
+ wrempty : OUT STD_LOGIC ;
+ wrfull : OUT STD_LOGIC
+ );
+end component;
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
2007-04-25 21:17:46 UTC (rev 5112)
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+FUNCTION fifo_512
+(
+ aclr,
+ data[15..0],
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq
+)
+
+RETURNS (
+ q[15..0],
+ rdempty,
+ rdfull,
+ wrempty,
+ wrfull
+);
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
2007-04-25 21:17:46 UTC (rev 5112)
@@ -0,0 +1,2977 @@
+// megafunction wizard: %LPM_FIFO+%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_512.v
+// Megafunction Name(s):
+// dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE"
DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" LPM_WIDTH=16
LPM_WIDTHU=8 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" aclr
data q rdclk rdempty rdfull rdreq wrclk wrempty wrfull wrreq
lpm_hint="RAM_BLOCK_TYPE=M4K" RAM_BLOCK_TYPE="M4K"
ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+//VERSION_BEGIN 5.1 cbx_a_gray2bin 2005:04:26:17:26:10:SJ cbx_a_graycounter
2005:07:26:16:56:48:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram
2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_dcfifo
2005:09:17:09:58:04:SJ cbx_fifo_common 2005:07:21:10:40:24:SJ cbx_flex10ke
2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare
2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode
2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl
2006:01:12:16:15:18:SJ cbx_scfifo 2005:09:06:13:25:24:SJ cbx_stratix
2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl
2005:09:12:10:23:22:SJ VERSION_END
+
+
+//a_fefifo LPM_NUMWORDS=256 lpm_widthad=8 OVERFLOW_CHECKING="ON"
UNDERFLOW_CHECKING="ON" USEDW_IN_DELAY=1 aclr clock empty full rreq usedw_in
+//VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_fifo_common
2005:07:21:10:40:24:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare
2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode
2005:04:27:14:28:48:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix
2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ VERSION_END
+
+
+//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES"
ageb dataa datab
+//VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub
2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_mgl
2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii
2005:11:02:10:43:56:SJ VERSION_END
+
+//synthesis_resources = lut 17
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_a_fefifo_gtc
+ (
+ aclr,
+ clock,
+ empty,
+ full,
+ rreq,
+ usedw_in) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clock;
+ output empty;
+ output full;
+ input rreq;
+ input [7:0] usedw_in;
+
+ reg b_full;
+ reg b_non_empty;
+ reg b_one;
+ reg llreq;
+ reg wire_cmp_full_aeb_int;
+ reg wire_cmp_full_agb_int;
+ wire wire_cmp_full_ageb;
+ wire [7:0] wire_cmp_full_dataa;
+ wire [7:0] wire_cmp_full_datab;
+ wire [7:0] equal_one;
+ wire [7:0] equal_two;
+ wire [7:0] equal_zero;
+ wire is_one0;
+ wire is_one1;
+ wire is_one2;
+ wire is_one3;
+ wire is_one4;
+ wire is_one5;
+ wire is_one6;
+ wire is_one7;
+ wire is_two0;
+ wire is_two1;
+ wire is_two2;
+ wire is_two3;
+ wire is_two4;
+ wire is_two5;
+ wire is_two6;
+ wire is_two7;
+ wire is_zero0;
+ wire is_zero1;
+ wire is_zero2;
+ wire is_zero3;
+ wire is_zero4;
+ wire is_zero5;
+ wire is_zero6;
+ wire is_zero7;
+ wire [7:0] usedw;
+
+ // synopsys translate_off
+ initial
+ b_full = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge aclr)
+ if (aclr == 1'b1) b_full <= 1'b0;
+ else b_full <= wire_cmp_full_ageb;
+ // synopsys translate_off
+ initial
+ b_non_empty = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge aclr)
+ if (aclr == 1'b1) b_non_empty <= 1'b0;
+ else b_non_empty <= (((b_non_empty & (b_non_empty ^ (((is_one7
& (~ llreq)) | (is_two7 & llreq)) & rreq))) | ((b_one & (~ is_zero7)) & (~
is_one7))) | (((~ b_one) & (~ b_non_empty)) & (~ is_zero7)));
+ // synopsys translate_off
+ initial
+ b_one = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge aclr)
+ if (aclr == 1'b1) b_one <= 1'b0;
+ else b_one <= ((~ b_one) & (b_non_empty & (((is_one7 & (~
llreq)) | (is_two7 & llreq)) & rreq)));
+ // synopsys translate_off
+ initial
+ llreq = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge aclr)
+ if (aclr == 1'b1) llreq <= 1'b0;
+ else llreq <= (rreq & b_non_empty);
+ always @(wire_cmp_full_dataa or wire_cmp_full_datab)
+ begin
+ if (wire_cmp_full_dataa == wire_cmp_full_datab)
+ begin
+ wire_cmp_full_aeb_int = 1'b1;
+ end
+ else
+ begin
+ wire_cmp_full_aeb_int = 1'b0;
+ end
+ if (wire_cmp_full_dataa > wire_cmp_full_datab)
+ begin
+ wire_cmp_full_agb_int = 1'b1;
+ end
+ else
+ begin
+ wire_cmp_full_agb_int = 1'b0;
+ end
+ end
+ assign
+ wire_cmp_full_ageb = wire_cmp_full_agb_int |
wire_cmp_full_aeb_int;
+ assign
+ wire_cmp_full_dataa = usedw,
+ wire_cmp_full_datab = 8'b11111101;
+ assign
+ empty = (~ b_non_empty),
+ equal_one = {{7{1'b1}}, 1'b0},
+ equal_two = {{6{1'b1}}, 1'b0, 1'b1},
+ equal_zero = {8{1'b1}},
+ full = b_full,
+ is_one0 = (usedw[0] ^ equal_one[0]),
+ is_one1 = ((usedw[1] ^ equal_one[1]) & is_one0),
+ is_one2 = ((usedw[2] ^ equal_one[2]) & is_one1),
+ is_one3 = ((usedw[3] ^ equal_one[3]) & is_one2),
+ is_one4 = ((usedw[4] ^ equal_one[4]) & is_one3),
+ is_one5 = ((usedw[5] ^ equal_one[5]) & is_one4),
+ is_one6 = ((usedw[6] ^ equal_one[6]) & is_one5),
+ is_one7 = ((usedw[7] ^ equal_one[7]) & is_one6),
+ is_two0 = (usedw[0] ^ equal_two[0]),
+ is_two1 = ((usedw[1] ^ equal_two[1]) & is_two0),
+ is_two2 = ((usedw[2] ^ equal_two[2]) & is_two1),
+ is_two3 = ((usedw[3] ^ equal_two[3]) & is_two2),
+ is_two4 = ((usedw[4] ^ equal_two[4]) & is_two3),
+ is_two5 = ((usedw[5] ^ equal_two[5]) & is_two4),
+ is_two6 = ((usedw[6] ^ equal_two[6]) & is_two5),
+ is_two7 = ((usedw[7] ^ equal_two[7]) & is_two6),
+ is_zero0 = (usedw[0] ^ equal_zero[0]),
+ is_zero1 = ((usedw[1] ^ equal_zero[1]) & is_zero0),
+ is_zero2 = ((usedw[2] ^ equal_zero[2]) & is_zero1),
+ is_zero3 = ((usedw[3] ^ equal_zero[3]) & is_zero2),
+ is_zero4 = ((usedw[4] ^ equal_zero[4]) & is_zero3),
+ is_zero5 = ((usedw[5] ^ equal_zero[5]) & is_zero4),
+ is_zero6 = ((usedw[6] ^ equal_zero[6]) & is_zero5),
+ is_zero7 = ((usedw[7] ^ equal_zero[7]) & is_zero6),
+ usedw = usedw_in;
+endmodule //fifo_512_a_fefifo_gtc
+
+
+//a_fefifo LPM_NUMWORDS=256 lpm_widthad=8 OVERFLOW_CHECKING="ON"
UNDERFLOW_CHECKING="ON" USEDW_IN_DELAY=1 aclr clock empty full usedw_in wreq
+//VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_fifo_common
2005:07:21:10:40:24:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare
2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode
2005:04:27:14:28:48:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix
2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ VERSION_END
+
+
+//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=8 ONE_INPUT_IS_CONSTANT="YES"
ageb dataa datab
+//VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub
2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_mgl
2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii
2005:11:02:10:43:56:SJ VERSION_END
+
+//synthesis_resources = lut 16
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_a_fefifo_ltc
+ (
+ aclr,
+ clock,
+ empty,
+ full,
+ usedw_in,
+ wreq) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clock;
+ output empty;
+ output full;
+ input [7:0] usedw_in;
+ input wreq;
+
+ reg b_full;
+ reg b_non_empty;
+ reg b_one;
+ reg wire_cmp_full_aeb_int;
+ reg wire_cmp_full_agb_int;
+ wire wire_cmp_full_ageb;
+ wire [7:0] wire_cmp_full_dataa;
+ wire [7:0] wire_cmp_full_datab;
+ wire [7:0] equal_zero;
+ wire is_zero0;
+ wire is_zero1;
+ wire is_zero2;
+ wire is_zero3;
+ wire is_zero4;
+ wire is_zero5;
+ wire is_zero6;
+ wire is_zero7;
+ wire [7:0] usedw;
+
+ // synopsys translate_off
+ initial
+ b_full = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge aclr)
+ if (aclr == 1'b1) b_full <= 1'b0;
+ else b_full <= wire_cmp_full_ageb;
+ // synopsys translate_off
+ initial
+ b_non_empty = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge aclr)
+ if (aclr == 1'b1) b_non_empty <= 1'b0;
+ else b_non_empty <= (wreq | (b_non_empty & ((~ b_one) | (~
is_zero7))));
+ // synopsys translate_off
+ initial
+ b_one = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge aclr)
+ if (aclr == 1'b1) b_one <= 1'b0;
+ else b_one <= ((b_one & (b_one ^ (wreq | is_zero7))) | (((~
b_one) & b_non_empty) & (~ wreq)));
+ always @(wire_cmp_full_dataa or wire_cmp_full_datab)
+ begin
+ if (wire_cmp_full_dataa == wire_cmp_full_datab)
+ begin
+ wire_cmp_full_aeb_int = 1'b1;
+ end
+ else
+ begin
+ wire_cmp_full_aeb_int = 1'b0;
+ end
+ if (wire_cmp_full_dataa > wire_cmp_full_datab)
+ begin
+ wire_cmp_full_agb_int = 1'b1;
+ end
+ else
+ begin
+ wire_cmp_full_agb_int = 1'b0;
+ end
+ end
+ assign
+ wire_cmp_full_ageb = wire_cmp_full_agb_int |
wire_cmp_full_aeb_int;
+ assign
+ wire_cmp_full_dataa = usedw,
+ wire_cmp_full_datab = 8'b11111101;
+ assign
+ empty = (~ b_non_empty),
+ equal_zero = {8{1'b1}},
+ full = b_full,
+ is_zero0 = (usedw[0] ^ equal_zero[0]),
+ is_zero1 = ((usedw[1] ^ equal_zero[1]) & is_zero0),
+ is_zero2 = ((usedw[2] ^ equal_zero[2]) & is_zero1),
+ is_zero3 = ((usedw[3] ^ equal_zero[3]) & is_zero2),
+ is_zero4 = ((usedw[4] ^ equal_zero[4]) & is_zero3),
+ is_zero5 = ((usedw[5] ^ equal_zero[5]) & is_zero4),
+ is_zero6 = ((usedw[6] ^ equal_zero[6]) & is_zero5),
+ is_zero7 = ((usedw[7] ^ equal_zero[7]) & is_zero6),
+ usedw = usedw_in;
+endmodule //fifo_512_a_fefifo_ltc
+
+
+//a_gray2bin device_family="Cyclone" WIDTH=8 bin gray
+//VERSION_BEGIN 5.1 cbx_a_gray2bin 2005:04:26:17:26:10:SJ cbx_mgl
2006:01:12:16:15:18:SJ VERSION_END
+
+//synthesis_resources =
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_a_gray2bin_uk4
+ (
+ bin,
+ gray) /* synthesis synthesis_clearbox=1 */;
+ output [7:0] bin;
+ input [7:0] gray;
+
+ wire xor0;
+ wire xor1;
+ wire xor2;
+ wire xor3;
+ wire xor4;
+ wire xor5;
+ wire xor6;
+
+ assign
+ bin = {gray[7], xor6, xor5, xor4, xor3, xor2, xor1, xor0},
+ xor0 = (gray[0] ^ xor1),
+ xor1 = (gray[1] ^ xor2),
+ xor2 = (gray[2] ^ xor3),
+ xor3 = (gray[3] ^ xor4),
+ xor4 = (gray[4] ^ xor5),
+ xor5 = (gray[5] ^ xor6),
+ xor6 = (gray[7] ^ gray[6]);
+endmodule //fifo_512_a_gray2bin_uk4
+
+
+//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=8 aclr clock cnt_en q
+//VERSION_BEGIN 5.1 cbx_a_gray2bin 2005:04:26:17:26:10:SJ cbx_a_graycounter
2005:07:26:16:56:48:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_flex10ke
2002:10:18:16:54:38:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix
2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ VERSION_END
+
+//synthesis_resources = lut 9
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_a_graycounter_t06
+ (
+ aclr,
+ clock,
+ cnt_en,
+ q) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clock;
+ input cnt_en;
+ output [7:0] q;
+
+ wire [0:0] wire_countera_0cout;
+ wire [0:0] wire_countera_1cout;
+ wire [0:0] wire_countera_2cout;
+ wire [0:0] wire_countera_3cout;
+ wire [0:0] wire_countera_4cout;
+ wire [0:0] wire_countera_5cout;
+ wire [0:0] wire_countera_6cout;
+ wire [7:0] wire_countera_regout;
+ wire wire_parity_cout;
+ wire wire_parity_regout;
+ wire [7:0] power_modified_counter_values;
+ wire sclr;
+ wire updown;
+
+ cyclone_lcell countera_0
+ (
+ .aclr(aclr),
+ .cin(wire_parity_cout),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_0cout[0:0]),
+ .dataa(cnt_en),
+ .datab(wire_countera_regout[0:0]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[0:0]),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_0.cin_used = "true",
+ countera_0.lut_mask = "c6a0",
+ countera_0.operation_mode = "arithmetic",
+ countera_0.sum_lutc_input = "cin",
+ countera_0.synch_mode = "on",
+ countera_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_1
+ (
+ .aclr(aclr),
+ .cin(wire_countera_0cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_1cout[0:0]),
+ .dataa(power_modified_counter_values[0]),
+ .datab(power_modified_counter_values[1]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[1:1]),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_1.cin_used = "true",
+ countera_1.lut_mask = "6c50",
+ countera_1.operation_mode = "arithmetic",
+ countera_1.sum_lutc_input = "cin",
+ countera_1.synch_mode = "on",
+ countera_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_2
+ (
+ .aclr(aclr),
+ .cin(wire_countera_1cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_2cout[0:0]),
+ .dataa(power_modified_counter_values[1]),
+ .datab(power_modified_counter_values[2]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[2:2]),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_2.cin_used = "true",
+ countera_2.lut_mask = "6c50",
+ countera_2.operation_mode = "arithmetic",
+ countera_2.sum_lutc_input = "cin",
+ countera_2.synch_mode = "on",
+ countera_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_3
+ (
+ .aclr(aclr),
+ .cin(wire_countera_2cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_3cout[0:0]),
+ .dataa(power_modified_counter_values[2]),
+ .datab(power_modified_counter_values[3]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[3:3]),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_3.cin_used = "true",
+ countera_3.lut_mask = "6c50",
+ countera_3.operation_mode = "arithmetic",
+ countera_3.sum_lutc_input = "cin",
+ countera_3.synch_mode = "on",
+ countera_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_4
+ (
+ .aclr(aclr),
+ .cin(wire_countera_3cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_4cout[0:0]),
+ .dataa(power_modified_counter_values[3]),
+ .datab(power_modified_counter_values[4]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[4:4]),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_4.cin_used = "true",
+ countera_4.lut_mask = "6c50",
+ countera_4.operation_mode = "arithmetic",
+ countera_4.sum_lutc_input = "cin",
+ countera_4.synch_mode = "on",
+ countera_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_5
+ (
+ .aclr(aclr),
+ .cin(wire_countera_4cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_5cout[0:0]),
+ .dataa(power_modified_counter_values[4]),
+ .datab(power_modified_counter_values[5]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[5:5]),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_5.cin_used = "true",
+ countera_5.lut_mask = "6c50",
+ countera_5.operation_mode = "arithmetic",
+ countera_5.sum_lutc_input = "cin",
+ countera_5.synch_mode = "on",
+ countera_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_6
+ (
+ .aclr(aclr),
+ .cin(wire_countera_5cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_countera_6cout[0:0]),
+ .dataa(power_modified_counter_values[5]),
+ .datab(power_modified_counter_values[6]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[6:6]),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_6.cin_used = "true",
+ countera_6.lut_mask = "6c50",
+ countera_6.operation_mode = "arithmetic",
+ countera_6.sum_lutc_input = "cin",
+ countera_6.synch_mode = "on",
+ countera_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell countera_7
+ (
+ .aclr(aclr),
+ .cin(wire_countera_6cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(),
+ .dataa(power_modified_counter_values[7]),
+ .ena(1'b1),
+ .regout(wire_countera_regout[7:7]),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datab(1'b1),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ countera_7.cin_used = "true",
+ countera_7.lut_mask = "5a5a",
+ countera_7.operation_mode = "normal",
+ countera_7.sum_lutc_input = "cin",
+ countera_7.synch_mode = "on",
+ countera_7.lpm_type = "cyclone_lcell";
+ cyclone_lcell parity
+ (
+ .aclr(aclr),
+ .cin(updown),
+ .clk(clock),
+ .combout(),
+ .cout(wire_parity_cout),
+ .dataa(cnt_en),
+ .datab(wire_parity_regout),
+ .ena(1'b1),
+ .regout(wire_parity_regout),
+ .sclr(sclr),
+ .aload(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ parity.cin_used = "true",
+ parity.lut_mask = "6682",
+ parity.operation_mode = "arithmetic",
+ parity.synch_mode = "on",
+ parity.lpm_type = "cyclone_lcell";
+ assign
+ power_modified_counter_values = {wire_countera_regout[7:0]},
+ q = power_modified_counter_values,
+ sclr = 1'b0,
+ updown = 1'b1;
+endmodule //fifo_512_a_graycounter_t06
+
+
+//altdpram DEVICE_FAMILY="Cyclone" lpm_hint="RAM_BLOCK_TYPE=M4K"
OUTDATA_REG="UNREGISTERED" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED"
SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=16 WIDTHAD=8 data
inclock outclock outclocken q rdaddress wraddress wren RAM_BLOCK_TYPE="M4K"
+//VERSION_BEGIN 5.1 cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram
2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub
2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_decode
2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl
2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii
2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ VERSION_END
+
+
+//altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE"
ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="NONE"
OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED"
RAM_BLOCK_TYPE="M4K" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0"
READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=16 WIDTH_B=16
WIDTH_BYTEENA_A=2 WIDTH_BYTEENA_B=2 WIDTHAD_A=8 WIDTHAD_B=8
WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b
wren_a
+//VERSION_BEGIN 5.1 cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii
2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare
2005:07:11:09:41:28:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux
2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix
2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl
2005:09:12:10:23:22:SJ VERSION_END
+
+//synthesis_resources = M4K 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_altsyncram_2fc1
+ (
+ address_a,
+ address_b,
+ clock0,
+ clock1,
+ clocken1,
+ data_a,
+ q_b,
+ wren_a) /* synthesis synthesis_clearbox=1 */
+ /* synthesis
ALTERA_ATTRIBUTE="OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION" */;
+ input [7:0] address_a;
+ input [7:0] address_b;
+ input clock0;
+ input clock1;
+ input clocken1;
+ input [15:0] data_a;
+ output [15:0] q_b;
+ input wren_a;
+
+ wire [0:0] wire_ram_block4a_0portbdataout;
+ wire [0:0] wire_ram_block4a_1portbdataout;
+ wire [0:0] wire_ram_block4a_2portbdataout;
+ wire [0:0] wire_ram_block4a_3portbdataout;
+ wire [0:0] wire_ram_block4a_4portbdataout;
+ wire [0:0] wire_ram_block4a_5portbdataout;
+ wire [0:0] wire_ram_block4a_6portbdataout;
+ wire [0:0] wire_ram_block4a_7portbdataout;
+ wire [0:0] wire_ram_block4a_8portbdataout;
+ wire [0:0] wire_ram_block4a_9portbdataout;
+ wire [0:0] wire_ram_block4a_10portbdataout;
+ wire [0:0] wire_ram_block4a_11portbdataout;
+ wire [0:0] wire_ram_block4a_12portbdataout;
+ wire [0:0] wire_ram_block4a_13portbdataout;
+ wire [0:0] wire_ram_block4a_14portbdataout;
+ wire [0:0] wire_ram_block4a_15portbdataout;
+ wire [7:0] address_a_wire;
+ wire [7:0] address_b_wire;
+
+ cyclone_ram_block ram_block4a_0
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[0]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_0portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_0.connectivity_checking = "OFF",
+ ram_block4a_0.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_0.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_0.operation_mode = "dual_port",
+ ram_block4a_0.port_a_address_clear = "none",
+ ram_block4a_0.port_a_address_width = 8,
+ ram_block4a_0.port_a_data_in_clear = "none",
+ ram_block4a_0.port_a_data_width = 1,
+ ram_block4a_0.port_a_first_address = 0,
+ ram_block4a_0.port_a_first_bit_number = 0,
+ ram_block4a_0.port_a_last_address = 255,
+ ram_block4a_0.port_a_logical_ram_depth = 256,
+ ram_block4a_0.port_a_logical_ram_width = 16,
+ ram_block4a_0.port_a_write_enable_clear = "none",
+ ram_block4a_0.port_b_address_clear = "none",
+ ram_block4a_0.port_b_address_clock = "clock1",
+ ram_block4a_0.port_b_address_width = 8,
+ ram_block4a_0.port_b_data_out_clear = "none",
+ ram_block4a_0.port_b_data_out_clock = "none",
+ ram_block4a_0.port_b_data_width = 1,
+ ram_block4a_0.port_b_first_address = 0,
+ ram_block4a_0.port_b_first_bit_number = 0,
+ ram_block4a_0.port_b_last_address = 255,
+ ram_block4a_0.port_b_logical_ram_depth = 256,
+ ram_block4a_0.port_b_logical_ram_width = 16,
+ ram_block4a_0.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_0.ram_block_type = "M4K",
+ ram_block4a_0.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_1
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[1]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_1portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_1.connectivity_checking = "OFF",
+ ram_block4a_1.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_1.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_1.operation_mode = "dual_port",
+ ram_block4a_1.port_a_address_clear = "none",
+ ram_block4a_1.port_a_address_width = 8,
+ ram_block4a_1.port_a_data_in_clear = "none",
+ ram_block4a_1.port_a_data_width = 1,
+ ram_block4a_1.port_a_first_address = 0,
+ ram_block4a_1.port_a_first_bit_number = 1,
+ ram_block4a_1.port_a_last_address = 255,
+ ram_block4a_1.port_a_logical_ram_depth = 256,
+ ram_block4a_1.port_a_logical_ram_width = 16,
+ ram_block4a_1.port_a_write_enable_clear = "none",
+ ram_block4a_1.port_b_address_clear = "none",
+ ram_block4a_1.port_b_address_clock = "clock1",
+ ram_block4a_1.port_b_address_width = 8,
+ ram_block4a_1.port_b_data_out_clear = "none",
+ ram_block4a_1.port_b_data_out_clock = "none",
+ ram_block4a_1.port_b_data_width = 1,
+ ram_block4a_1.port_b_first_address = 0,
+ ram_block4a_1.port_b_first_bit_number = 1,
+ ram_block4a_1.port_b_last_address = 255,
+ ram_block4a_1.port_b_logical_ram_depth = 256,
+ ram_block4a_1.port_b_logical_ram_width = 16,
+ ram_block4a_1.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_1.ram_block_type = "M4K",
+ ram_block4a_1.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_2
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[2]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_2portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_2.connectivity_checking = "OFF",
+ ram_block4a_2.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_2.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_2.operation_mode = "dual_port",
+ ram_block4a_2.port_a_address_clear = "none",
+ ram_block4a_2.port_a_address_width = 8,
+ ram_block4a_2.port_a_data_in_clear = "none",
+ ram_block4a_2.port_a_data_width = 1,
+ ram_block4a_2.port_a_first_address = 0,
+ ram_block4a_2.port_a_first_bit_number = 2,
+ ram_block4a_2.port_a_last_address = 255,
+ ram_block4a_2.port_a_logical_ram_depth = 256,
+ ram_block4a_2.port_a_logical_ram_width = 16,
+ ram_block4a_2.port_a_write_enable_clear = "none",
+ ram_block4a_2.port_b_address_clear = "none",
+ ram_block4a_2.port_b_address_clock = "clock1",
+ ram_block4a_2.port_b_address_width = 8,
+ ram_block4a_2.port_b_data_out_clear = "none",
+ ram_block4a_2.port_b_data_out_clock = "none",
+ ram_block4a_2.port_b_data_width = 1,
+ ram_block4a_2.port_b_first_address = 0,
+ ram_block4a_2.port_b_first_bit_number = 2,
+ ram_block4a_2.port_b_last_address = 255,
+ ram_block4a_2.port_b_logical_ram_depth = 256,
+ ram_block4a_2.port_b_logical_ram_width = 16,
+ ram_block4a_2.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_2.ram_block_type = "M4K",
+ ram_block4a_2.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_3
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[3]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_3portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_3.connectivity_checking = "OFF",
+ ram_block4a_3.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_3.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_3.operation_mode = "dual_port",
+ ram_block4a_3.port_a_address_clear = "none",
+ ram_block4a_3.port_a_address_width = 8,
+ ram_block4a_3.port_a_data_in_clear = "none",
+ ram_block4a_3.port_a_data_width = 1,
+ ram_block4a_3.port_a_first_address = 0,
+ ram_block4a_3.port_a_first_bit_number = 3,
+ ram_block4a_3.port_a_last_address = 255,
+ ram_block4a_3.port_a_logical_ram_depth = 256,
+ ram_block4a_3.port_a_logical_ram_width = 16,
+ ram_block4a_3.port_a_write_enable_clear = "none",
+ ram_block4a_3.port_b_address_clear = "none",
+ ram_block4a_3.port_b_address_clock = "clock1",
+ ram_block4a_3.port_b_address_width = 8,
+ ram_block4a_3.port_b_data_out_clear = "none",
+ ram_block4a_3.port_b_data_out_clock = "none",
+ ram_block4a_3.port_b_data_width = 1,
+ ram_block4a_3.port_b_first_address = 0,
+ ram_block4a_3.port_b_first_bit_number = 3,
+ ram_block4a_3.port_b_last_address = 255,
+ ram_block4a_3.port_b_logical_ram_depth = 256,
+ ram_block4a_3.port_b_logical_ram_width = 16,
+ ram_block4a_3.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_3.ram_block_type = "M4K",
+ ram_block4a_3.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_4
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[4]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_4portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_4.connectivity_checking = "OFF",
+ ram_block4a_4.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_4.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_4.operation_mode = "dual_port",
+ ram_block4a_4.port_a_address_clear = "none",
+ ram_block4a_4.port_a_address_width = 8,
+ ram_block4a_4.port_a_data_in_clear = "none",
+ ram_block4a_4.port_a_data_width = 1,
+ ram_block4a_4.port_a_first_address = 0,
+ ram_block4a_4.port_a_first_bit_number = 4,
+ ram_block4a_4.port_a_last_address = 255,
+ ram_block4a_4.port_a_logical_ram_depth = 256,
+ ram_block4a_4.port_a_logical_ram_width = 16,
+ ram_block4a_4.port_a_write_enable_clear = "none",
+ ram_block4a_4.port_b_address_clear = "none",
+ ram_block4a_4.port_b_address_clock = "clock1",
+ ram_block4a_4.port_b_address_width = 8,
+ ram_block4a_4.port_b_data_out_clear = "none",
+ ram_block4a_4.port_b_data_out_clock = "none",
+ ram_block4a_4.port_b_data_width = 1,
+ ram_block4a_4.port_b_first_address = 0,
+ ram_block4a_4.port_b_first_bit_number = 4,
+ ram_block4a_4.port_b_last_address = 255,
+ ram_block4a_4.port_b_logical_ram_depth = 256,
+ ram_block4a_4.port_b_logical_ram_width = 16,
+ ram_block4a_4.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_4.ram_block_type = "M4K",
+ ram_block4a_4.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_5
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[5]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_5portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_5.connectivity_checking = "OFF",
+ ram_block4a_5.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_5.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_5.operation_mode = "dual_port",
+ ram_block4a_5.port_a_address_clear = "none",
+ ram_block4a_5.port_a_address_width = 8,
+ ram_block4a_5.port_a_data_in_clear = "none",
+ ram_block4a_5.port_a_data_width = 1,
+ ram_block4a_5.port_a_first_address = 0,
+ ram_block4a_5.port_a_first_bit_number = 5,
+ ram_block4a_5.port_a_last_address = 255,
+ ram_block4a_5.port_a_logical_ram_depth = 256,
+ ram_block4a_5.port_a_logical_ram_width = 16,
+ ram_block4a_5.port_a_write_enable_clear = "none",
+ ram_block4a_5.port_b_address_clear = "none",
+ ram_block4a_5.port_b_address_clock = "clock1",
+ ram_block4a_5.port_b_address_width = 8,
+ ram_block4a_5.port_b_data_out_clear = "none",
+ ram_block4a_5.port_b_data_out_clock = "none",
+ ram_block4a_5.port_b_data_width = 1,
+ ram_block4a_5.port_b_first_address = 0,
+ ram_block4a_5.port_b_first_bit_number = 5,
+ ram_block4a_5.port_b_last_address = 255,
+ ram_block4a_5.port_b_logical_ram_depth = 256,
+ ram_block4a_5.port_b_logical_ram_width = 16,
+ ram_block4a_5.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_5.ram_block_type = "M4K",
+ ram_block4a_5.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_6
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[6]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_6portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_6.connectivity_checking = "OFF",
+ ram_block4a_6.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_6.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_6.operation_mode = "dual_port",
+ ram_block4a_6.port_a_address_clear = "none",
+ ram_block4a_6.port_a_address_width = 8,
+ ram_block4a_6.port_a_data_in_clear = "none",
+ ram_block4a_6.port_a_data_width = 1,
+ ram_block4a_6.port_a_first_address = 0,
+ ram_block4a_6.port_a_first_bit_number = 6,
+ ram_block4a_6.port_a_last_address = 255,
+ ram_block4a_6.port_a_logical_ram_depth = 256,
+ ram_block4a_6.port_a_logical_ram_width = 16,
+ ram_block4a_6.port_a_write_enable_clear = "none",
+ ram_block4a_6.port_b_address_clear = "none",
+ ram_block4a_6.port_b_address_clock = "clock1",
+ ram_block4a_6.port_b_address_width = 8,
+ ram_block4a_6.port_b_data_out_clear = "none",
+ ram_block4a_6.port_b_data_out_clock = "none",
+ ram_block4a_6.port_b_data_width = 1,
+ ram_block4a_6.port_b_first_address = 0,
+ ram_block4a_6.port_b_first_bit_number = 6,
+ ram_block4a_6.port_b_last_address = 255,
+ ram_block4a_6.port_b_logical_ram_depth = 256,
+ ram_block4a_6.port_b_logical_ram_width = 16,
+ ram_block4a_6.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_6.ram_block_type = "M4K",
+ ram_block4a_6.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_7
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[7]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_7portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_7.connectivity_checking = "OFF",
+ ram_block4a_7.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_7.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_7.operation_mode = "dual_port",
+ ram_block4a_7.port_a_address_clear = "none",
+ ram_block4a_7.port_a_address_width = 8,
+ ram_block4a_7.port_a_data_in_clear = "none",
+ ram_block4a_7.port_a_data_width = 1,
+ ram_block4a_7.port_a_first_address = 0,
+ ram_block4a_7.port_a_first_bit_number = 7,
+ ram_block4a_7.port_a_last_address = 255,
+ ram_block4a_7.port_a_logical_ram_depth = 256,
+ ram_block4a_7.port_a_logical_ram_width = 16,
+ ram_block4a_7.port_a_write_enable_clear = "none",
+ ram_block4a_7.port_b_address_clear = "none",
+ ram_block4a_7.port_b_address_clock = "clock1",
+ ram_block4a_7.port_b_address_width = 8,
+ ram_block4a_7.port_b_data_out_clear = "none",
+ ram_block4a_7.port_b_data_out_clock = "none",
+ ram_block4a_7.port_b_data_width = 1,
+ ram_block4a_7.port_b_first_address = 0,
+ ram_block4a_7.port_b_first_bit_number = 7,
+ ram_block4a_7.port_b_last_address = 255,
+ ram_block4a_7.port_b_logical_ram_depth = 256,
+ ram_block4a_7.port_b_logical_ram_width = 16,
+ ram_block4a_7.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_7.ram_block_type = "M4K",
+ ram_block4a_7.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_8
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[8]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_8portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_8.connectivity_checking = "OFF",
+ ram_block4a_8.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_8.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_8.operation_mode = "dual_port",
+ ram_block4a_8.port_a_address_clear = "none",
+ ram_block4a_8.port_a_address_width = 8,
+ ram_block4a_8.port_a_data_in_clear = "none",
+ ram_block4a_8.port_a_data_width = 1,
+ ram_block4a_8.port_a_first_address = 0,
+ ram_block4a_8.port_a_first_bit_number = 8,
+ ram_block4a_8.port_a_last_address = 255,
+ ram_block4a_8.port_a_logical_ram_depth = 256,
+ ram_block4a_8.port_a_logical_ram_width = 16,
+ ram_block4a_8.port_a_write_enable_clear = "none",
+ ram_block4a_8.port_b_address_clear = "none",
+ ram_block4a_8.port_b_address_clock = "clock1",
+ ram_block4a_8.port_b_address_width = 8,
+ ram_block4a_8.port_b_data_out_clear = "none",
+ ram_block4a_8.port_b_data_out_clock = "none",
+ ram_block4a_8.port_b_data_width = 1,
+ ram_block4a_8.port_b_first_address = 0,
+ ram_block4a_8.port_b_first_bit_number = 8,
+ ram_block4a_8.port_b_last_address = 255,
+ ram_block4a_8.port_b_logical_ram_depth = 256,
+ ram_block4a_8.port_b_logical_ram_width = 16,
+ ram_block4a_8.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_8.ram_block_type = "M4K",
+ ram_block4a_8.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_9
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[9]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_9portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_9.connectivity_checking = "OFF",
+ ram_block4a_9.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_9.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_9.operation_mode = "dual_port",
+ ram_block4a_9.port_a_address_clear = "none",
+ ram_block4a_9.port_a_address_width = 8,
+ ram_block4a_9.port_a_data_in_clear = "none",
+ ram_block4a_9.port_a_data_width = 1,
+ ram_block4a_9.port_a_first_address = 0,
+ ram_block4a_9.port_a_first_bit_number = 9,
+ ram_block4a_9.port_a_last_address = 255,
+ ram_block4a_9.port_a_logical_ram_depth = 256,
+ ram_block4a_9.port_a_logical_ram_width = 16,
+ ram_block4a_9.port_a_write_enable_clear = "none",
+ ram_block4a_9.port_b_address_clear = "none",
+ ram_block4a_9.port_b_address_clock = "clock1",
+ ram_block4a_9.port_b_address_width = 8,
+ ram_block4a_9.port_b_data_out_clear = "none",
+ ram_block4a_9.port_b_data_out_clock = "none",
+ ram_block4a_9.port_b_data_width = 1,
+ ram_block4a_9.port_b_first_address = 0,
+ ram_block4a_9.port_b_first_bit_number = 9,
+ ram_block4a_9.port_b_last_address = 255,
+ ram_block4a_9.port_b_logical_ram_depth = 256,
+ ram_block4a_9.port_b_logical_ram_width = 16,
+ ram_block4a_9.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_9.ram_block_type = "M4K",
+ ram_block4a_9.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_10
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[10]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_10portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_10.connectivity_checking = "OFF",
+ ram_block4a_10.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_10.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_10.operation_mode = "dual_port",
+ ram_block4a_10.port_a_address_clear = "none",
+ ram_block4a_10.port_a_address_width = 8,
+ ram_block4a_10.port_a_data_in_clear = "none",
+ ram_block4a_10.port_a_data_width = 1,
+ ram_block4a_10.port_a_first_address = 0,
+ ram_block4a_10.port_a_first_bit_number = 10,
+ ram_block4a_10.port_a_last_address = 255,
+ ram_block4a_10.port_a_logical_ram_depth = 256,
+ ram_block4a_10.port_a_logical_ram_width = 16,
+ ram_block4a_10.port_a_write_enable_clear = "none",
+ ram_block4a_10.port_b_address_clear = "none",
+ ram_block4a_10.port_b_address_clock = "clock1",
+ ram_block4a_10.port_b_address_width = 8,
+ ram_block4a_10.port_b_data_out_clear = "none",
+ ram_block4a_10.port_b_data_out_clock = "none",
+ ram_block4a_10.port_b_data_width = 1,
+ ram_block4a_10.port_b_first_address = 0,
+ ram_block4a_10.port_b_first_bit_number = 10,
+ ram_block4a_10.port_b_last_address = 255,
+ ram_block4a_10.port_b_logical_ram_depth = 256,
+ ram_block4a_10.port_b_logical_ram_width = 16,
+ ram_block4a_10.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_10.ram_block_type = "M4K",
+ ram_block4a_10.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_11
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[11]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_11portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_11.connectivity_checking = "OFF",
+ ram_block4a_11.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_11.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_11.operation_mode = "dual_port",
+ ram_block4a_11.port_a_address_clear = "none",
+ ram_block4a_11.port_a_address_width = 8,
+ ram_block4a_11.port_a_data_in_clear = "none",
+ ram_block4a_11.port_a_data_width = 1,
+ ram_block4a_11.port_a_first_address = 0,
+ ram_block4a_11.port_a_first_bit_number = 11,
+ ram_block4a_11.port_a_last_address = 255,
+ ram_block4a_11.port_a_logical_ram_depth = 256,
+ ram_block4a_11.port_a_logical_ram_width = 16,
+ ram_block4a_11.port_a_write_enable_clear = "none",
+ ram_block4a_11.port_b_address_clear = "none",
+ ram_block4a_11.port_b_address_clock = "clock1",
+ ram_block4a_11.port_b_address_width = 8,
+ ram_block4a_11.port_b_data_out_clear = "none",
+ ram_block4a_11.port_b_data_out_clock = "none",
+ ram_block4a_11.port_b_data_width = 1,
+ ram_block4a_11.port_b_first_address = 0,
+ ram_block4a_11.port_b_first_bit_number = 11,
+ ram_block4a_11.port_b_last_address = 255,
+ ram_block4a_11.port_b_logical_ram_depth = 256,
+ ram_block4a_11.port_b_logical_ram_width = 16,
+ ram_block4a_11.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_11.ram_block_type = "M4K",
+ ram_block4a_11.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_12
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[12]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_12portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_12.connectivity_checking = "OFF",
+ ram_block4a_12.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_12.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_12.operation_mode = "dual_port",
+ ram_block4a_12.port_a_address_clear = "none",
+ ram_block4a_12.port_a_address_width = 8,
+ ram_block4a_12.port_a_data_in_clear = "none",
+ ram_block4a_12.port_a_data_width = 1,
+ ram_block4a_12.port_a_first_address = 0,
+ ram_block4a_12.port_a_first_bit_number = 12,
+ ram_block4a_12.port_a_last_address = 255,
+ ram_block4a_12.port_a_logical_ram_depth = 256,
+ ram_block4a_12.port_a_logical_ram_width = 16,
+ ram_block4a_12.port_a_write_enable_clear = "none",
+ ram_block4a_12.port_b_address_clear = "none",
+ ram_block4a_12.port_b_address_clock = "clock1",
+ ram_block4a_12.port_b_address_width = 8,
+ ram_block4a_12.port_b_data_out_clear = "none",
+ ram_block4a_12.port_b_data_out_clock = "none",
+ ram_block4a_12.port_b_data_width = 1,
+ ram_block4a_12.port_b_first_address = 0,
+ ram_block4a_12.port_b_first_bit_number = 12,
+ ram_block4a_12.port_b_last_address = 255,
+ ram_block4a_12.port_b_logical_ram_depth = 256,
+ ram_block4a_12.port_b_logical_ram_width = 16,
+ ram_block4a_12.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_12.ram_block_type = "M4K",
+ ram_block4a_12.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_13
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[13]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_13portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_13.connectivity_checking = "OFF",
+ ram_block4a_13.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_13.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_13.operation_mode = "dual_port",
+ ram_block4a_13.port_a_address_clear = "none",
+ ram_block4a_13.port_a_address_width = 8,
+ ram_block4a_13.port_a_data_in_clear = "none",
+ ram_block4a_13.port_a_data_width = 1,
+ ram_block4a_13.port_a_first_address = 0,
+ ram_block4a_13.port_a_first_bit_number = 13,
+ ram_block4a_13.port_a_last_address = 255,
+ ram_block4a_13.port_a_logical_ram_depth = 256,
+ ram_block4a_13.port_a_logical_ram_width = 16,
+ ram_block4a_13.port_a_write_enable_clear = "none",
+ ram_block4a_13.port_b_address_clear = "none",
+ ram_block4a_13.port_b_address_clock = "clock1",
+ ram_block4a_13.port_b_address_width = 8,
+ ram_block4a_13.port_b_data_out_clear = "none",
+ ram_block4a_13.port_b_data_out_clock = "none",
+ ram_block4a_13.port_b_data_width = 1,
+ ram_block4a_13.port_b_first_address = 0,
+ ram_block4a_13.port_b_first_bit_number = 13,
+ ram_block4a_13.port_b_last_address = 255,
+ ram_block4a_13.port_b_logical_ram_depth = 256,
+ ram_block4a_13.port_b_logical_ram_width = 16,
+ ram_block4a_13.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_13.ram_block_type = "M4K",
+ ram_block4a_13.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_14
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[14]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_14portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_14.connectivity_checking = "OFF",
+ ram_block4a_14.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_14.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_14.operation_mode = "dual_port",
+ ram_block4a_14.port_a_address_clear = "none",
+ ram_block4a_14.port_a_address_width = 8,
+ ram_block4a_14.port_a_data_in_clear = "none",
+ ram_block4a_14.port_a_data_width = 1,
+ ram_block4a_14.port_a_first_address = 0,
+ ram_block4a_14.port_a_first_bit_number = 14,
+ ram_block4a_14.port_a_last_address = 255,
+ ram_block4a_14.port_a_logical_ram_depth = 256,
+ ram_block4a_14.port_a_logical_ram_width = 16,
+ ram_block4a_14.port_a_write_enable_clear = "none",
+ ram_block4a_14.port_b_address_clear = "none",
+ ram_block4a_14.port_b_address_clock = "clock1",
+ ram_block4a_14.port_b_address_width = 8,
+ ram_block4a_14.port_b_data_out_clear = "none",
+ ram_block4a_14.port_b_data_out_clock = "none",
+ ram_block4a_14.port_b_data_width = 1,
+ ram_block4a_14.port_b_first_address = 0,
+ ram_block4a_14.port_b_first_bit_number = 14,
+ ram_block4a_14.port_b_last_address = 255,
+ ram_block4a_14.port_b_logical_ram_depth = 256,
+ ram_block4a_14.port_b_logical_ram_width = 16,
+ ram_block4a_14.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_14.ram_block_type = "M4K",
+ ram_block4a_14.lpm_type = "cyclone_ram_block";
+ cyclone_ram_block ram_block4a_15
+ (
+ .clk0(clock0),
+ .clk1(clock1),
+ .ena0(wren_a),
+ .ena1(clocken1),
+ .portaaddr({address_a_wire[7:0]}),
+ .portadatain({data_a[15]}),
+ .portadataout(),
+ .portawe(1'b1),
+ .portbaddr({address_b_wire[7:0]}),
+ .portbdataout(wire_ram_block4a_15portbdataout[0:0]),
+ .portbrewe(1'b1)
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_off
+ `endif
+ ,
+ .clr0(1'b0),
+ .clr1(1'b0),
+ .portabyteenamasks({1{1'b1}}),
+ .portbbyteenamasks({1{1'b1}}),
+ .portbdatain({1{1'b0}})
+ `ifdef FORMAL_VERIFICATION
+ `else
+ // synopsys translate_on
+ `endif
+ // synopsys translate_off
+ ,
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ ram_block4a_15.connectivity_checking = "OFF",
+ ram_block4a_15.logical_ram_name = "ALTSYNCRAM",
+ ram_block4a_15.mixed_port_feed_through_mode = "dont_care",
+ ram_block4a_15.operation_mode = "dual_port",
+ ram_block4a_15.port_a_address_clear = "none",
+ ram_block4a_15.port_a_address_width = 8,
+ ram_block4a_15.port_a_data_in_clear = "none",
+ ram_block4a_15.port_a_data_width = 1,
+ ram_block4a_15.port_a_first_address = 0,
+ ram_block4a_15.port_a_first_bit_number = 15,
+ ram_block4a_15.port_a_last_address = 255,
+ ram_block4a_15.port_a_logical_ram_depth = 256,
+ ram_block4a_15.port_a_logical_ram_width = 16,
+ ram_block4a_15.port_a_write_enable_clear = "none",
+ ram_block4a_15.port_b_address_clear = "none",
+ ram_block4a_15.port_b_address_clock = "clock1",
+ ram_block4a_15.port_b_address_width = 8,
+ ram_block4a_15.port_b_data_out_clear = "none",
+ ram_block4a_15.port_b_data_out_clock = "none",
+ ram_block4a_15.port_b_data_width = 1,
+ ram_block4a_15.port_b_first_address = 0,
+ ram_block4a_15.port_b_first_bit_number = 15,
+ ram_block4a_15.port_b_last_address = 255,
+ ram_block4a_15.port_b_logical_ram_depth = 256,
+ ram_block4a_15.port_b_logical_ram_width = 16,
+ ram_block4a_15.port_b_read_enable_write_enable_clock = "clock1",
+ ram_block4a_15.ram_block_type = "M4K",
+ ram_block4a_15.lpm_type = "cyclone_ram_block";
+ assign
+ address_a_wire = address_a,
+ address_b_wire = address_b,
+ q_b = {wire_ram_block4a_15portbdataout[0],
wire_ram_block4a_14portbdataout[0], wire_ram_block4a_13portbdataout[0],
wire_ram_block4a_12portbdataout[0], wire_ram_block4a_11portbdataout[0],
wire_ram_block4a_10portbdataout[0], wire_ram_block4a_9portbdataout[0],
wire_ram_block4a_8portbdataout[0], wire_ram_block4a_7portbdataout[0],
wire_ram_block4a_6portbdataout[0], wire_ram_block4a_5portbdataout[0],
wire_ram_block4a_4portbdataout[0], wire_ram_block4a_3portbdataout[0],
wire_ram_block4a_2portbdataout[0], wire_ram_block4a_1portbdataout[0],
wire_ram_block4a_0portbdataout[0]};
+endmodule //fifo_512_altsyncram_2fc1
+
+//synthesis_resources = M4K 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_dpram_vdr
+ (
+ data,
+ inclock,
+ outclock,
+ outclocken,
+ q,
+ rdaddress,
+ wraddress,
+ wren) /* synthesis synthesis_clearbox=1 */;
+ input [15:0] data;
+ input inclock;
+ input outclock;
+ input outclocken;
+ output [15:0] q;
+ input [7:0] rdaddress;
+ input [7:0] wraddress;
+ input wren;
+
+ wire [15:0] wire_altsyncram3_q_b;
+
+ fifo_512_altsyncram_2fc1 altsyncram3
+ (
+ .address_a(wraddress),
+ .address_b(rdaddress),
+ .clock0(inclock),
+ .clock1(outclock),
+ .clocken1(outclocken),
+ .data_a(data),
+ .q_b(wire_altsyncram3_q_b),
+ .wren_a(wren));
+ assign
+ q = wire_altsyncram3_q_b;
+endmodule //fifo_512_dpram_vdr
+
+
+//dffpipe DELAY=1 WIDTH=8 clock clrn d q
ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+//VERSION_BEGIN 5.1 cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratixii
2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ VERSION_END
+
+//synthesis_resources = lut 8
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_dffpipe_fd9
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis
ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+ input clock;
+ input clrn;
+ input [7:0] d;
+ output [7:0] q;
+
+ reg [7:0] dffe5a;
+ wire ena;
+ wire prn;
+ wire sclr;
+
+ // synopsys translate_off
+ initial
+ dffe5a = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe5a <= {8{1'b1}};
+ else if (clrn == 1'b0) dffe5a <= 8'b0;
+ else if (ena == 1'b1) dffe5a <= (d & {8{(~ sclr)}});
+ assign
+ ena = 1'b1,
+ prn = 1'b1,
+ q = dffe5a,
+ sclr = 1'b0;
+endmodule //fifo_512_dffpipe_fd9
+
+
+//dffpipe DELAY=3 WIDTH=8 clock clrn d q
ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF
+//VERSION_BEGIN 5.1 cbx_a_gray2bin 2005:04:26:17:26:10:SJ cbx_a_graycounter
2005:07:26:16:56:48:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram
2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_dcfifo
2005:09:17:09:58:04:SJ cbx_fifo_common 2005:07:21:10:40:24:SJ cbx_flex10ke
2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare
2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode
2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl
2006:01:12:16:15:18:SJ cbx_scfifo 2005:09:06:13:25:24:SJ cbx_stratix
2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl
2005:09:12:10:23:22:SJ VERSION_END
+
+
+//dffpipe DELAY=3 WIDTH=8 clock clrn d q
ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+//VERSION_BEGIN 5.1 cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratixii
2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ VERSION_END
+
+//synthesis_resources = lut 24
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_dffpipe_hd9
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis
ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+ input clock;
+ input clrn;
+ input [7:0] d;
+ output [7:0] q;
+
+ reg [7:0] dffe7a;
+ reg [7:0] dffe8a;
+ reg [7:0] dffe9a;
+ wire ena;
+ wire prn;
+ wire sclr;
+
+ // synopsys translate_off
+ initial
+ dffe7a = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe7a <= {8{1'b1}};
+ else if (clrn == 1'b0) dffe7a <= 8'b0;
+ else if (ena == 1'b1) dffe7a <= (d & {8{(~ sclr)}});
+ // synopsys translate_off
+ initial
+ dffe8a = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe8a <= {8{1'b1}};
+ else if (clrn == 1'b0) dffe8a <= 8'b0;
+ else if (ena == 1'b1) dffe8a <= (dffe7a & {8{(~ sclr)}});
+ // synopsys translate_off
+ initial
+ dffe9a = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe9a <= {8{1'b1}};
+ else if (clrn == 1'b0) dffe9a <= 8'b0;
+ else if (ena == 1'b1) dffe9a <= (dffe8a & {8{(~ sclr)}});
+ assign
+ ena = 1'b1,
+ prn = 1'b1,
+ q = dffe9a,
+ sclr = 1'b0;
+endmodule //fifo_512_dffpipe_hd9
+
+//synthesis_resources = lut 24
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_alt_synch_pipe_nc8
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
+ input clock;
+ input clrn;
+ input [7:0] d;
+ output [7:0] q;
+
+ wire [7:0] wire_dffpipe6_q;
+
+ fifo_512_dffpipe_hd9 dffpipe6
+ (
+ .clock(clock),
+ .clrn(clrn),
+ .d(d),
+ .q(wire_dffpipe6_q));
+ assign
+ q = wire_dffpipe6_q;
+endmodule //fifo_512_alt_synch_pipe_nc8
+
+
+//dffpipe DELAY=3 WIDTH=8 clock clrn d q
ALTERA_INTERNAL_OPTIONS=X_ON_VIOLATION_OPTION=OFF
+//VERSION_BEGIN 5.1 cbx_a_gray2bin 2005:04:26:17:26:10:SJ cbx_a_graycounter
2005:07:26:16:56:48:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram
2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_dcfifo
2005:09:17:09:58:04:SJ cbx_fifo_common 2005:07:21:10:40:24:SJ cbx_flex10ke
2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare
2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode
2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl
2006:01:12:16:15:18:SJ cbx_scfifo 2005:09:06:13:25:24:SJ cbx_stratix
2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl
2005:09:12:10:23:22:SJ VERSION_END
+
+
+//dffpipe DELAY=3 WIDTH=8 clock clrn d q
ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
+//VERSION_BEGIN 5.1 cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratixii
2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ VERSION_END
+
+//synthesis_resources = lut 24
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_dffpipe_id9
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis
ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+ input clock;
+ input clrn;
+ input [7:0] d;
+ output [7:0] q;
+
+ reg [7:0] dffe11a;
+ reg [7:0] dffe12a;
+ reg [7:0] dffe13a;
+ wire ena;
+ wire prn;
+ wire sclr;
+
+ // synopsys translate_off
+ initial
+ dffe11a = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe11a <= {8{1'b1}};
+ else if (clrn == 1'b0) dffe11a <= 8'b0;
+ else if (ena == 1'b1) dffe11a <= (d & {8{(~ sclr)}});
+ // synopsys translate_off
+ initial
+ dffe12a = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe12a <= {8{1'b1}};
+ else if (clrn == 1'b0) dffe12a <= 8'b0;
+ else if (ena == 1'b1) dffe12a <= (dffe11a & {8{(~ sclr)}});
+ // synopsys translate_off
+ initial
+ dffe13a = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or negedge prn or negedge clrn)
+ if (prn == 1'b0) dffe13a <= {8{1'b1}};
+ else if (clrn == 1'b0) dffe13a <= 8'b0;
+ else if (ena == 1'b1) dffe13a <= (dffe12a & {8{(~ sclr)}});
+ assign
+ ena = 1'b1,
+ prn = 1'b1,
+ q = dffe13a,
+ sclr = 1'b0;
+endmodule //fifo_512_dffpipe_id9
+
+//synthesis_resources = lut 24
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_alt_synch_pipe_oc8
+ (
+ clock,
+ clrn,
+ d,
+ q) /* synthesis synthesis_clearbox=1 */
+ /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
+ input clock;
+ input clrn;
+ input [7:0] d;
+ output [7:0] q;
+
+ wire [7:0] wire_dffpipe10_q;
+
+ fifo_512_dffpipe_id9 dffpipe10
+ (
+ .clock(clock),
+ .clrn(clrn),
+ .d(d),
+ .q(wire_dffpipe10_q));
+ assign
+ q = wire_dffpipe10_q;
+endmodule //fifo_512_alt_synch_pipe_oc8
+
+
+//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=8 dataa
datab result
+//VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub
2005:11:02:10:42:42:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix
2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ VERSION_END
+
+//synthesis_resources = lut 8
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_add_sub_008
+ (
+ dataa,
+ datab,
+ result) /* synthesis synthesis_clearbox=1 */;
+ input [7:0] dataa;
+ input [7:0] datab;
+ output [7:0] result;
+
+ wire [7:0] wire_add_sub_cella_combout;
+ wire [0:0] wire_add_sub_cella_0cout;
+ wire [0:0] wire_add_sub_cella_1cout;
+ wire [0:0] wire_add_sub_cella_2cout;
+ wire [0:0] wire_add_sub_cella_3cout;
+ wire [0:0] wire_add_sub_cella_4cout;
+ wire [0:0] wire_add_sub_cella_5cout;
+ wire [0:0] wire_add_sub_cella_6cout;
+ wire [7:0] wire_add_sub_cella_dataa;
+ wire [7:0] wire_add_sub_cella_datab;
+
+ cyclone_lcell add_sub_cella_0
+ (
+ .cin(1'b1),
+ .combout(wire_add_sub_cella_combout[0:0]),
+ .cout(wire_add_sub_cella_0cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[0:0]),
+ .datab(wire_add_sub_cella_datab[0:0]),
+ .regout(),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_0.cin_used = "true",
+ add_sub_cella_0.lut_mask = "69b2",
+ add_sub_cella_0.operation_mode = "arithmetic",
+ add_sub_cella_0.sum_lutc_input = "cin",
+ add_sub_cella_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_1
+ (
+ .cin(wire_add_sub_cella_0cout[0:0]),
+ .combout(wire_add_sub_cella_combout[1:1]),
+ .cout(wire_add_sub_cella_1cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[1:1]),
+ .datab(wire_add_sub_cella_datab[1:1]),
+ .regout(),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_1.cin_used = "true",
+ add_sub_cella_1.lut_mask = "69b2",
+ add_sub_cella_1.operation_mode = "arithmetic",
+ add_sub_cella_1.sum_lutc_input = "cin",
+ add_sub_cella_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_2
+ (
+ .cin(wire_add_sub_cella_1cout[0:0]),
+ .combout(wire_add_sub_cella_combout[2:2]),
+ .cout(wire_add_sub_cella_2cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[2:2]),
+ .datab(wire_add_sub_cella_datab[2:2]),
+ .regout(),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_2.cin_used = "true",
+ add_sub_cella_2.lut_mask = "69b2",
+ add_sub_cella_2.operation_mode = "arithmetic",
+ add_sub_cella_2.sum_lutc_input = "cin",
+ add_sub_cella_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_3
+ (
+ .cin(wire_add_sub_cella_2cout[0:0]),
+ .combout(wire_add_sub_cella_combout[3:3]),
+ .cout(wire_add_sub_cella_3cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[3:3]),
+ .datab(wire_add_sub_cella_datab[3:3]),
+ .regout(),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_3.cin_used = "true",
+ add_sub_cella_3.lut_mask = "69b2",
+ add_sub_cella_3.operation_mode = "arithmetic",
+ add_sub_cella_3.sum_lutc_input = "cin",
+ add_sub_cella_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_4
+ (
+ .cin(wire_add_sub_cella_3cout[0:0]),
+ .combout(wire_add_sub_cella_combout[4:4]),
+ .cout(wire_add_sub_cella_4cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[4:4]),
+ .datab(wire_add_sub_cella_datab[4:4]),
+ .regout(),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_4.cin_used = "true",
+ add_sub_cella_4.lut_mask = "69b2",
+ add_sub_cella_4.operation_mode = "arithmetic",
+ add_sub_cella_4.sum_lutc_input = "cin",
+ add_sub_cella_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_5
+ (
+ .cin(wire_add_sub_cella_4cout[0:0]),
+ .combout(wire_add_sub_cella_combout[5:5]),
+ .cout(wire_add_sub_cella_5cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[5:5]),
+ .datab(wire_add_sub_cella_datab[5:5]),
+ .regout(),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_5.cin_used = "true",
+ add_sub_cella_5.lut_mask = "69b2",
+ add_sub_cella_5.operation_mode = "arithmetic",
+ add_sub_cella_5.sum_lutc_input = "cin",
+ add_sub_cella_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_6
+ (
+ .cin(wire_add_sub_cella_5cout[0:0]),
+ .combout(wire_add_sub_cella_combout[6:6]),
+ .cout(wire_add_sub_cella_6cout[0:0]),
+ .dataa(wire_add_sub_cella_dataa[6:6]),
+ .datab(wire_add_sub_cella_datab[6:6]),
+ .regout(),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_6.cin_used = "true",
+ add_sub_cella_6.lut_mask = "69b2",
+ add_sub_cella_6.operation_mode = "arithmetic",
+ add_sub_cella_6.sum_lutc_input = "cin",
+ add_sub_cella_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell add_sub_cella_7
+ (
+ .cin(wire_add_sub_cella_6cout[0:0]),
+ .combout(wire_add_sub_cella_combout[7:7]),
+ .cout(),
+ .dataa(wire_add_sub_cella_dataa[7:7]),
+ .datab(wire_add_sub_cella_datab[7:7]),
+ .regout(),
+ .aclr(1'b0),
+ .aload(1'b0),
+ .clk(1'b0),
+ .datac(1'b1),
+ .datad(1'b1),
+ .ena(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0),
+ .sclr(1'b0),
+ .sload(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ add_sub_cella_7.cin_used = "true",
+ add_sub_cella_7.lut_mask = "6969",
+ add_sub_cella_7.operation_mode = "normal",
+ add_sub_cella_7.sum_lutc_input = "cin",
+ add_sub_cella_7.lpm_type = "cyclone_lcell";
+ assign
+ wire_add_sub_cella_dataa = dataa,
+ wire_add_sub_cella_datab = datab;
+ assign
+ result = wire_add_sub_cella_combout;
+endmodule //fifo_512_add_sub_008
+
+
+//lpm_counter DEVICE_FAMILY="Cyclone" lpm_direction="UP" lpm_width=8 aclr
clock cnt_en q
+//VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub
2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_counter
2005:08:23:15:49:38:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_mgl
2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii
2005:11:02:10:43:56:SJ VERSION_END
+
+//synthesis_resources = lut 8
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_cntr_9v7
+ (
+ aclr,
+ clock,
+ cnt_en,
+ q) /* synthesis synthesis_clearbox=1 */;
+ input aclr;
+ input clock;
+ input cnt_en;
+ output [7:0] q;
+
+ wire [0:0] wire_counter_cella_0cout;
+ wire [0:0] wire_counter_cella_1cout;
+ wire [0:0] wire_counter_cella_2cout;
+ wire [0:0] wire_counter_cella_3cout;
+ wire [0:0] wire_counter_cella_4cout;
+ wire [0:0] wire_counter_cella_5cout;
+ wire [0:0] wire_counter_cella_6cout;
+ wire [7:0] wire_counter_cella_dataa;
+ wire [7:0] wire_counter_cella_datac;
+ wire [7:0] wire_counter_cella_regout;
+ wire aclr_actual;
+ wire clk_en;
+ wire [7:0] data;
+ wire [7:0] s_val;
+ wire [7:0] safe_q;
+ wire sclr;
+ wire sload;
+ wire sset;
+ wire sset_node;
+
+ cyclone_lcell counter_cella_0
+ (
+ .aclr(aclr_actual),
+ .aload(1'b0),
+ .clk(clock),
+ .combout(),
+ .cout(wire_counter_cella_0cout[0:0]),
+ .dataa(wire_counter_cella_dataa[0:0]),
+ .datab(cnt_en),
+ .datac(wire_counter_cella_datac[0:0]),
+ .ena(clk_en),
+ .regout(wire_counter_cella_regout[0:0]),
+ .sclr(sclr),
+ .sload((sset_node | sload)),
+ .cin(1'b0),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ counter_cella_0.cin_used = "false",
+ counter_cella_0.lut_mask = "66aa",
+ counter_cella_0.operation_mode = "arithmetic",
+ counter_cella_0.synch_mode = "on",
+ counter_cella_0.lpm_type = "cyclone_lcell";
+ cyclone_lcell counter_cella_1
+ (
+ .aclr(aclr_actual),
+ .aload(1'b0),
+ .cin(wire_counter_cella_0cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_counter_cella_1cout[0:0]),
+ .dataa(wire_counter_cella_dataa[1:1]),
+ .datab(cnt_en),
+ .datac(wire_counter_cella_datac[1:1]),
+ .ena(clk_en),
+ .regout(wire_counter_cella_regout[1:1]),
+ .sclr(sclr),
+ .sload((sset_node | sload)),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ counter_cella_1.cin_used = "true",
+ counter_cella_1.lut_mask = "6aa0",
+ counter_cella_1.operation_mode = "arithmetic",
+ counter_cella_1.sum_lutc_input = "cin",
+ counter_cella_1.synch_mode = "on",
+ counter_cella_1.lpm_type = "cyclone_lcell";
+ cyclone_lcell counter_cella_2
+ (
+ .aclr(aclr_actual),
+ .aload(1'b0),
+ .cin(wire_counter_cella_1cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_counter_cella_2cout[0:0]),
+ .dataa(wire_counter_cella_dataa[2:2]),
+ .datab(cnt_en),
+ .datac(wire_counter_cella_datac[2:2]),
+ .ena(clk_en),
+ .regout(wire_counter_cella_regout[2:2]),
+ .sclr(sclr),
+ .sload((sset_node | sload)),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ counter_cella_2.cin_used = "true",
+ counter_cella_2.lut_mask = "6aa0",
+ counter_cella_2.operation_mode = "arithmetic",
+ counter_cella_2.sum_lutc_input = "cin",
+ counter_cella_2.synch_mode = "on",
+ counter_cella_2.lpm_type = "cyclone_lcell";
+ cyclone_lcell counter_cella_3
+ (
+ .aclr(aclr_actual),
+ .aload(1'b0),
+ .cin(wire_counter_cella_2cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_counter_cella_3cout[0:0]),
+ .dataa(wire_counter_cella_dataa[3:3]),
+ .datab(cnt_en),
+ .datac(wire_counter_cella_datac[3:3]),
+ .ena(clk_en),
+ .regout(wire_counter_cella_regout[3:3]),
+ .sclr(sclr),
+ .sload((sset_node | sload)),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ counter_cella_3.cin_used = "true",
+ counter_cella_3.lut_mask = "6aa0",
+ counter_cella_3.operation_mode = "arithmetic",
+ counter_cella_3.sum_lutc_input = "cin",
+ counter_cella_3.synch_mode = "on",
+ counter_cella_3.lpm_type = "cyclone_lcell";
+ cyclone_lcell counter_cella_4
+ (
+ .aclr(aclr_actual),
+ .aload(1'b0),
+ .cin(wire_counter_cella_3cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_counter_cella_4cout[0:0]),
+ .dataa(wire_counter_cella_dataa[4:4]),
+ .datab(cnt_en),
+ .datac(wire_counter_cella_datac[4:4]),
+ .ena(clk_en),
+ .regout(wire_counter_cella_regout[4:4]),
+ .sclr(sclr),
+ .sload((sset_node | sload)),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ counter_cella_4.cin_used = "true",
+ counter_cella_4.lut_mask = "6aa0",
+ counter_cella_4.operation_mode = "arithmetic",
+ counter_cella_4.sum_lutc_input = "cin",
+ counter_cella_4.synch_mode = "on",
+ counter_cella_4.lpm_type = "cyclone_lcell";
+ cyclone_lcell counter_cella_5
+ (
+ .aclr(aclr_actual),
+ .aload(1'b0),
+ .cin(wire_counter_cella_4cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_counter_cella_5cout[0:0]),
+ .dataa(wire_counter_cella_dataa[5:5]),
+ .datab(cnt_en),
+ .datac(wire_counter_cella_datac[5:5]),
+ .ena(clk_en),
+ .regout(wire_counter_cella_regout[5:5]),
+ .sclr(sclr),
+ .sload((sset_node | sload)),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ counter_cella_5.cin_used = "true",
+ counter_cella_5.lut_mask = "6aa0",
+ counter_cella_5.operation_mode = "arithmetic",
+ counter_cella_5.sum_lutc_input = "cin",
+ counter_cella_5.synch_mode = "on",
+ counter_cella_5.lpm_type = "cyclone_lcell";
+ cyclone_lcell counter_cella_6
+ (
+ .aclr(aclr_actual),
+ .aload(1'b0),
+ .cin(wire_counter_cella_5cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(wire_counter_cella_6cout[0:0]),
+ .dataa(wire_counter_cella_dataa[6:6]),
+ .datab(cnt_en),
+ .datac(wire_counter_cella_datac[6:6]),
+ .ena(clk_en),
+ .regout(wire_counter_cella_regout[6:6]),
+ .sclr(sclr),
+ .sload((sset_node | sload)),
+ .datad(1'b1),
+ .inverta(1'b0),
+ .regcascin(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ counter_cella_6.cin_used = "true",
+ counter_cella_6.lut_mask = "6aa0",
+ counter_cella_6.operation_mode = "arithmetic",
+ counter_cella_6.sum_lutc_input = "cin",
+ counter_cella_6.synch_mode = "on",
+ counter_cella_6.lpm_type = "cyclone_lcell";
+ cyclone_lcell counter_cella_7
+ (
+ .aclr(aclr_actual),
+ .aload(1'b0),
+ .cin(wire_counter_cella_6cout[0:0]),
+ .clk(clock),
+ .combout(),
+ .cout(),
+ .dataa(wire_counter_cella_dataa[7:7]),
+ .datab(cnt_en),
+ .datac(wire_counter_cella_datac[7:7]),
+ .datad(1'b1),
+ .ena(clk_en),
+ .regout(wire_counter_cella_regout[7:7]),
+ .sclr(sclr),
+ .sload((sset_node | sload)),
+ .inverta(1'b0),
+ .regcascin(1'b0)
+ // synopsys translate_off
+ ,
+ .cin0(),
+ .cin1(),
+ .cout0(),
+ .cout1(),
+ .devclrn(),
+ .devpor()
+ // synopsys translate_on
+ );
+ defparam
+ counter_cella_7.cin_used = "true",
+ counter_cella_7.lut_mask = "6aa0",
+ counter_cella_7.operation_mode = "normal",
+ counter_cella_7.sum_lutc_input = "cin",
+ counter_cella_7.synch_mode = "on",
+ counter_cella_7.lpm_type = "cyclone_lcell";
+ assign
+ wire_counter_cella_dataa = safe_q,
+ wire_counter_cella_datac = (({8{sset}} & s_val) | ({8{(~
sset)}} & data));
+ assign
+ aclr_actual = aclr,
+ clk_en = 1'b1,
+ data = {8{1'b0}},
+ q = safe_q,
+ s_val = 8'b11111111,
+ safe_q = wire_counter_cella_regout,
+ sclr = 1'b0,
+ sload = 1'b0,
+ sset = 1'b0,
+ sset_node = 1'b0;
+endmodule //fifo_512_cntr_9v7
+
+//synthesis_resources = lut 122 M4K 1
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module fifo_512_dcfifo_gq41
+ (
+ aclr,
+ data,
+ q,
+ rdclk,
+ rdempty,
+ rdfull,
+ rdreq,
+ rdusedw,
+ wrclk,
+ wrempty,
+ wrfull,
+ wrreq,
+ wrusedw) /* synthesis synthesis_clearbox=1 */
+ /* synthesis
ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;suppress_da_rule_internal=d101;suppress_da_rule_internal=d102;{
-from \"write_delay_cycle\" -to \"dffpipe_rs_dgwp|dffpipe6|dffe7a\" }CUT=ON;{
-from \"rdptr_g|power_modified_counter_values\" -to
\"dffpipe_ws_dgrp|dffpipe10|dffe11a\" }CUT=ON" */;
+ input aclr;
+ input [15:0] data;
+ output [15:0] q;
+ input rdclk;
+ output rdempty;
+ output rdfull;
+ input rdreq;
+ output [7:0] rdusedw;
+ input wrclk;
+ output wrempty;
+ output wrfull;
+ input wrreq;
+ output [7:0] wrusedw;
+
+ wire wire_read_state_empty;
+ wire wire_read_state_full;
+ wire wire_write_state_empty;
+ wire wire_write_state_full;
+ wire [7:0] wire_gray2bin_rs_nbwp_bin;
+ wire [7:0] wire_gray2bin_ws_nbrp_bin;
+ wire [7:0] wire_rdptr_g_q;
+ wire [7:0] wire_wrptr_g_q;
+ wire [15:0] wire_fiforam_q;
+ reg [7:0] write_delay_cycle;
+ wire [7:0] wire_dffpipe_rdbuw_q;
+ wire [7:0] wire_dffpipe_rdusedw_q;
+ wire [7:0] wire_dffpipe_rs_dbwp_q;
+ wire [7:0] wire_dffpipe_rs_dgwp_q;
+ wire [7:0] wire_dffpipe_wr_dbuw_q;
+ wire [7:0] wire_dffpipe_wrusedw_q;
+ wire [7:0] wire_dffpipe_ws_dgrp_q;
+ wire [7:0] wire_dffpipe_ws_nbrp_q;
+ wire [7:0] wire_lpm_add_sub_rd_udwn_result;
+ wire [7:0] wire_lpm_add_sub_wr_udwn_result;
+ wire [7:0] wire_rdptr_b_q;
+ wire [7:0] wire_wrptr_b_q;
+ wire [7:0] rd_dbuw;
+ wire [7:0] rd_udwn;
+ wire [7:0] rs_dbwp;
+ wire [7:0] rs_dgwp;
+ wire [7:0] rs_nbwp;
+ wire tmp_aclr;
+ wire [7:0] tmp_data;
+ wire valid_rreq;
+ wire valid_wreq;
+ wire [7:0] wr_dbuw;
+ wire [7:0] wr_udwn;
+ wire [7:0] ws_dbrp;
+ wire [7:0] ws_dgrp;
+ wire [7:0] ws_nbrp;
+
+ fifo_512_a_fefifo_gtc read_state
+ (
+ .aclr(aclr),
+ .clock(rdclk),
+ .empty(wire_read_state_empty),
+ .full(wire_read_state_full),
+ .rreq(rdreq),
+ .usedw_in(rd_dbuw));
+ fifo_512_a_fefifo_ltc write_state
+ (
+ .aclr(aclr),
+ .clock(wrclk),
+ .empty(wire_write_state_empty),
+ .full(wire_write_state_full),
+ .usedw_in(wr_dbuw),
+ .wreq(wrreq));
+ fifo_512_a_gray2bin_uk4 gray2bin_rs_nbwp
+ (
+ .bin(wire_gray2bin_rs_nbwp_bin),
+ .gray(rs_dgwp));
+ fifo_512_a_gray2bin_uk4 gray2bin_ws_nbrp
+ (
+ .bin(wire_gray2bin_ws_nbrp_bin),
+ .gray(ws_dgrp));
+ fifo_512_a_graycounter_t06 rdptr_g
+ (
+ .aclr(aclr),
+ .clock(rdclk),
+ .cnt_en(valid_rreq),
+ .q(wire_rdptr_g_q));
+ fifo_512_a_graycounter_t06 wrptr_g
+ (
+ .aclr(aclr),
+ .clock(wrclk),
+ .cnt_en(valid_wreq),
+ .q(wire_wrptr_g_q));
+ fifo_512_dpram_vdr fiforam
+ (
+ .data(data),
+ .inclock(wrclk),
+ .outclock(rdclk),
+ .outclocken(valid_rreq),
+ .q(wire_fiforam_q),
+ .rdaddress(wire_rdptr_g_q),
+ .wraddress(wire_wrptr_g_q),
+ .wren(valid_wreq));
+ // synopsys translate_off
+ initial
+ write_delay_cycle = 0;
+ // synopsys translate_on
+ always @ ( posedge wrclk or posedge aclr)
+ if (aclr == 1'b1) write_delay_cycle <= 8'b0;
+ else write_delay_cycle <= wire_wrptr_g_q;
+ fifo_512_dffpipe_fd9 dffpipe_rdbuw
+ (
+ .clock(rdclk),
+ .clrn(tmp_aclr),
+ .d(rd_udwn),
+ .q(wire_dffpipe_rdbuw_q));
+ fifo_512_dffpipe_fd9 dffpipe_rdusedw
+ (
+ .clock(rdclk),
+ .clrn(tmp_aclr),
+ .d(rd_udwn),
+ .q(wire_dffpipe_rdusedw_q));
+ fifo_512_dffpipe_fd9 dffpipe_rs_dbwp
+ (
+ .clock(rdclk),
+ .clrn(tmp_aclr),
+ .d(rs_nbwp),
+ .q(wire_dffpipe_rs_dbwp_q));
+ fifo_512_alt_synch_pipe_nc8 dffpipe_rs_dgwp
+ (
+ .clock(rdclk),
+ .clrn(tmp_aclr),
+ .d(write_delay_cycle),
+ .q(wire_dffpipe_rs_dgwp_q));
+ fifo_512_dffpipe_fd9 dffpipe_wr_dbuw
+ (
+ .clock(wrclk),
+ .clrn(tmp_aclr),
+ .d(wr_udwn),
+ .q(wire_dffpipe_wr_dbuw_q));
+ fifo_512_dffpipe_fd9 dffpipe_wrusedw
+ (
+ .clock(wrclk),
+ .clrn(tmp_aclr),
+ .d(wr_udwn),
+ .q(wire_dffpipe_wrusedw_q));
+ fifo_512_alt_synch_pipe_oc8 dffpipe_ws_dgrp
+ (
+ .clock(wrclk),
+ .clrn(tmp_aclr),
+ .d(tmp_data),
+ .q(wire_dffpipe_ws_dgrp_q));
+ fifo_512_dffpipe_fd9 dffpipe_ws_nbrp
+ (
+ .clock(wrclk),
+ .clrn(tmp_aclr),
+ .d(ws_nbrp),
+ .q(wire_dffpipe_ws_nbrp_q));
+ fifo_512_add_sub_008 lpm_add_sub_rd_udwn
+ (
+ .dataa(rs_dbwp),
+ .datab(wire_rdptr_b_q),
+ .result(wire_lpm_add_sub_rd_udwn_result));
+ fifo_512_add_sub_008 lpm_add_sub_wr_udwn
+ (
+ .dataa(wire_wrptr_b_q),
+ .datab(ws_dbrp),
+ .result(wire_lpm_add_sub_wr_udwn_result));
+ fifo_512_cntr_9v7 rdptr_b
+ (
+ .aclr(aclr),
+ .clock(rdclk),
+ .cnt_en(valid_rreq),
+ .q(wire_rdptr_b_q));
+ fifo_512_cntr_9v7 wrptr_b
+ (
+ .aclr(aclr),
+ .clock(wrclk),
+ .cnt_en(valid_wreq),
+ .q(wire_wrptr_b_q));
+ assign
+ q = wire_fiforam_q,
+ rd_dbuw = wire_dffpipe_rdbuw_q,
+ rd_udwn = wire_lpm_add_sub_rd_udwn_result,
+ rdempty = wire_read_state_empty,
+ rdfull = wire_read_state_full,
+ rdusedw = wire_dffpipe_rdusedw_q,
+ rs_dbwp = wire_dffpipe_rs_dbwp_q,
+ rs_dgwp = wire_dffpipe_rs_dgwp_q,
+ rs_nbwp = wire_gray2bin_rs_nbwp_bin,
+ tmp_aclr = (~ aclr),
+ tmp_data = wire_rdptr_g_q,
+ valid_rreq = (rdreq & (~ wire_read_state_empty)),
+ valid_wreq = (wrreq & (~ wire_write_state_full)),
+ wr_dbuw = wire_dffpipe_wr_dbuw_q,
+ wr_udwn = wire_lpm_add_sub_wr_udwn_result,
+ wrempty = wire_write_state_empty,
+ wrfull = wire_write_state_full,
+ wrusedw = wire_dffpipe_wrusedw_q,
+ ws_dbrp = wire_dffpipe_ws_nbrp_q,
+ ws_dgrp = wire_dffpipe_ws_dgrp_q,
+ ws_nbrp = wire_gray2bin_ws_nbrp_bin;
+endmodule //fifo_512_dcfifo_gq41
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_512 (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdfull,
+ wrempty,
+ wrfull)/* synthesis synthesis_clearbox = 1 */;
+
+ input aclr;
+ input [15:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [15:0] q;
+ output rdempty;
+ output rdfull;
+ output wrempty;
+ output wrfull;
+
+ wire sub_wire0;
+ wire sub_wire1;
+ wire sub_wire2;
+ wire sub_wire3;
+ wire [15:0] sub_wire4;
+ wire rdfull = sub_wire0;
+ wire rdempty = sub_wire1;
+ wire wrfull = sub_wire2;
+ wire wrempty = sub_wire3;
+ wire [15:0] q = sub_wire4[15:0];
+
+ fifo_512_dcfifo_gq41 fifo_512_dcfifo_gq41_component (
+ .wrclk (wrclk),
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .rdclk (rdclk),
+ .wrreq (wrreq),
+ .data (data),
+ .rdfull (sub_wire0),
+ .rdempty (sub_wire1),
+ .wrfull (sub_wire2),
+ .wrempty (sub_wire3),
+ .q (sub_wire4));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_wave*.jpg FALSE
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
2007-04-25 21:17:46 UTC (rev 5112)
@@ -0,0 +1,132 @@
+// megafunction wizard: %LPM_FIFO+%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo
+
+// ============================================================
+// File Name: fifo_512.v
+// Megafunction Name(s):
+// dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module fifo_512 (
+ aclr,
+ data,
+ rdclk,
+ rdreq,
+ wrclk,
+ wrreq,
+ q,
+ rdempty,
+ rdfull,
+ wrempty,
+ wrfull)/* synthesis synthesis_clearbox = 1 */;
+
+ input aclr;
+ input [15:0] data;
+ input rdclk;
+ input rdreq;
+ input wrclk;
+ input wrreq;
+ output [15:0] q;
+ output rdempty;
+ output rdfull;
+ output wrempty;
+ output wrfull;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_wave*.jpg FALSE
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
___________________________________________________________________
Name: svn:executable
+ *
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-25
20:15:46 UTC (rev 5111)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-25
21:17:46 UTC (rev 5112)
@@ -243,35 +243,39 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 14
+Project_Files_Count = 16
Project_File_0 = ./strobe_gen_test.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
10 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_1 = ./fake_fx2.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177429364 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = Z:/wc/inband/usrp/fpga/megacells/fifo_512.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272423 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273481 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_5 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177369489 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = ./chan_fifo_readers_test.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_7 = Z:/wc/simulations/fake_fx2_test.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
12 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_8 = ./usb_packet_fifo_test.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_9 = ./tx_buffer_test.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177348942 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_10 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177366318 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_11 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365862 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1175362687 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_13 = ./usb_fifo_reader_test.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = ./usb_packet_fifo2_test.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177530454 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = ./fake_fx2_test.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = ./fake_fx2.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177517843 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177530505 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272423 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273481 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177369489 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = ./chan_fifo_readers_test.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = ./usb_packet_fifo_test.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_10 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365862 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_11 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177366318 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_12 = ./tx_buffer_test.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177348942 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_13 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1175362687 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = ./usb_fifo_reader_test.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_15 = ../inband/usrp/fpga/megacells/fifo_512.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177531735 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -301,6 +305,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/simulations/fake_fx2.v 0 0} {Z:/wc/simulations/fake_fx2_test.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/strobe_gen.v 0 0} {Z:/wc/usb_packet_fifo.v 0 1}
+EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1
Added: gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
2007-04-25 21:17:46 UTC (rev 5112)
@@ -0,0 +1,84 @@
+module usb_packet_fifo2_test();
+
+ //Inputs
+ reg reset ;
+ reg usb_clock ;
+ reg fpga_clock ;
+ reg skip_packet ;
+ reg write_enable ;
+ reg read_enable ;
+ reg [15:0]write_data ;
+
+ //Ouputs
+ wire [15:0]read_data ;
+ wire have_space ;
+ wire tx_empty ;
+ wire pkt_waiting ;
+
+ reg [15:0] i ;
+
+ usb_packet_fifo2 usb_fifo (
+ .reset (reset),
+ .usb_clock (usb_clock),
+ .fpga_clock (fpga_clock),
+ .have_space (have_space),
+ .pkt_waiting (pkt_waiting),
+ .tx_empty (tx_empty),
+ .write_enable (write_enable),
+ .skip_packet (skip_enable),
+ .read_data (read_data),
+ .write_data (write_data) ) ;
+
+ initial begin
+ reset = 1 ;
+ usb_clock = 0 ;
+ fpga_clock = 0 ;
+ skip_packet = 0 ;
+ write_enable = 0 ;
+ read_enable = 0 ;
+ i = 0 ;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge usb_clock)
+ reset = 1'b0 ;
+ end
+
+ // Write an entire packets worth of data
+ // into the FIFO
+ repeat (256) begin
+ @(posedge usb_clock)
+ write_enable = 1'b1 ;
+ write_data = i ;
+ i = i + 1 ;
+ end
+ @(posedge usb_clock)
+ write_enable = 1'b0 ;
+
+ // Only read the first 10 bytes of data
+ repeat (10) begin
+ @(posedge fpga_clock)
+ read_enable = 1'b1 ;
+ end
+ @(posedge fpga_clock)
+ read_enable = 1'b0 ;
+
+ // Skip the rest of the packet
+ @(posedge fpga_clock)
+ skip_packet = 1'b1 ;
+ @(posedge fpga_clock)
+ skip_packet = 1'b0 ;
+
+ end
+
+
+ always
+ #5 usb_clock = ~usb_clock;
+
+ always
+ #2 fpga_clock = ~fpga_clock;
+
+endmodule
Property changes on:
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
___________________________________________________________________
Name: svn:executable
+ *
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