[Commit-gnuradio] r5120 - in gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog: . CVS

[matt]

Author: matt
Date: 2007-04-26 01:29:34 -0600 (Thu, 26 Apr 2007)
New Revision: 5120

Modified:
   gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
   
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
Log:
minor update from OpenCores CVS for fixing simulation with iverilog


Modified: 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
--- 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries    
    2007-04-26 02:05:03 UTC (rev 5119)
+++ 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries    
    2007-04-26 07:29:34 UTC (rev 5120)
@@ -5,5 +5,5 @@
 /aeMB_aslu.v/1.5/Wed Apr 25 19:45:17 2007//
 /aeMB_core.v/1.4/Wed Apr 25 19:45:17 2007//
 /aeMB_decode.v/1.5/Wed Apr 25 19:45:17 2007//
-/aeMB_regfile.v/1.9/Wed Apr 25 19:45:17 2007//
+/aeMB_regfile.v/1.10/Thu Apr 26 07:28:30 2007//
 D

Modified: 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
--- 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v 
    2007-04-26 02:05:03 UTC (rev 5119)
+++ 
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v 
    2007-04-26 07:29:34 UTC (rev 5120)
@@ -1,5 +1,5 @@
 /*
- * $Id: aeMB_regfile.v,v 1.9 2007/04/25 22:15:04 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.10 2007/04/25 22:52:53 sybreon Exp $
  * 
  * AEMB Register File
  * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
  *
  * HISTORY
  * $Log: aeMB_regfile.v,v $
+ * Revision 1.10  2007/04/25 22:52:53  sybreon
+ * Fixed minor simulation bug.
+ *
  * Revision 1.9  2007/04/25 22:15:04  sybreon
  * Added support for 8-bit and 16-bit data types.
  *
@@ -120,12 +123,12 @@
    always @(/*AUTOSENSE*/rDWBSEL or wDWBDAT)
      case (rDWBSEL)      
        4'hF: sDWBDAT <= wDWBDAT;
-       4'hC: sDWBDAT <= {(16){1'b0},wDWBDAT[31:16]};
-       4'h3: sDWBDAT <= {(16){1'b0},wDWBDAT[15:0]};
-       4'h8: sDWBDAT <= {(24){1'b0},wDWBDAT[31:24]};
-       4'h4: sDWBDAT <= {(24){1'b0},wDWBDAT[23:16]};
-       4'h2: sDWBDAT <= {(24){1'b0},wDWBDAT[15:8]};
-       4'h1: sDWBDAT <= {(24){1'b0},wDWBDAT[7:0]};       
+       4'hC: sDWBDAT <= {16'd0,wDWBDAT[31:16]};
+       4'h3: sDWBDAT <= {16'd0,wDWBDAT[15:0]};
+       4'h8: sDWBDAT <= {24'd0,wDWBDAT[31:24]};
+       4'h4: sDWBDAT <= {24'd0,wDWBDAT[23:16]};
+       4'h2: sDWBDAT <= {24'd0,wDWBDAT[15:8]};
+       4'h1: sDWBDAT <= {24'd0,wDWBDAT[7:0]};      
        default: sDWBDAT <= 32'h0;       
      endcase // case (rDWBSEL)