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[Commit-gnuradio] r5194 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
|
Subject: |
[Commit-gnuradio] r5194 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim/verilog sim/verilog/CVS sw sw/CVS sw/c sw/c/CVS |
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Date: |
Mon, 30 Apr 2007 16:36:25 -0600 (MDT) |
Author: matt
Date: 2007-04-30 16:36:24 -0600 (Mon, 30 Apr 2007)
New Revision: 5194
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
Log:
latest CVS of aemb, includes data hazard fix and is now properly big endian
without the wrapper
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-04-30 18:02:39 UTC (rev 5193)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,9 +1,9 @@
/aeMB_ucore.v/1.1/Fri Apr 13 13:02:34 2007//
/aeMB_wbbus.v/1.1/Fri Apr 13 13:02:34 2007//
-/aeMB_aslu.v/1.7/Fri Apr 27 01:14:55 2007//
/aeMB_control.v/1.4/Fri Apr 27 01:14:55 2007//
/aeMB_core.v/1.5/Fri Apr 27 01:14:55 2007//
/aeMB_fetch.v/1.4/Fri Apr 27 01:14:55 2007//
-/aeMB_decode.v/1.7/Fri Apr 27 02:01:26 2007//
-/aeMB_regfile.v/1.14/Sat Apr 28 20:01:41 2007//
+/aeMB_aslu.v/1.8/Mon Apr 30 17:31:53 2007//
+/aeMB_decode.v/1.8/Mon Apr 30 17:31:54 2007//
+/aeMB_regfile.v/1.15/Mon Apr 30 17:31:54 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-04-30 18:02:39 UTC (rev 5193)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_aslu.v,v 1.7 2007/04/27 00:23:55 sybreon Exp $
+ * $Id: aeMB_aslu.v,v 1.8 2007/04/30 15:56:50 sybreon Exp $
*
* AEMB Arithmetic Shift Logic Unit
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_aslu.v,v $
+ * Revision 1.8 2007/04/30 15:56:50 sybreon
+ * Removed byte acrobatics.
+ *
* Revision 1.7 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
@@ -61,7 +64,6 @@
output [DSIZ-1:0] dwb_adr_o;
output [3:0] dwb_sel_o;
- //input [31:0] dwb_dat_i;
output [31:0] rRESULT;
output [3:0] rDWBSEL;
@@ -213,7 +215,7 @@
reg [3:0] rDWBSEL, xDWBSEL;
assign dwb_adr_o = {rRESULT[DSIZ-1:2],2'b00};
- assign dwb_sel_o = {rDWBSEL[0],rDWBSEL[1],rDWBSEL[2],rDWBSEL[3]};
+ assign dwb_sel_o = rDWBSEL;
always @(/*AUTOSENSE*/rOPC or wADD)
case (wADD[1:0])
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
2007-04-30 18:02:39 UTC (rev 5193)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core_BE.v
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,8 +1,9 @@
// Wrapper for aeMB core:
-// Make it big-endian like the standard MicroBlaze
// Drive wb_cyc_o (just tied to wb_stb_o for now)
// Make input reset active high (like the signal name makes it sound....)
+// No longer needed
+// Make it big-endian like the standard MicroBlaze
module aeMB_core_BE
#(parameter ISIZ=32, parameter DSIZ=32)
@@ -35,16 +36,28 @@
.iwb_stb_o(iwb_stb_o),
.iwb_adr_o(iwb_adr_o),
.iwb_ack_i(iwb_ack_i),
- .iwb_dat_i({iwb_dat_i[7:0],
- iwb_dat_i[15:8],
- iwb_dat_i[23:16],
- iwb_dat_i[31:24]}),
-
+ .iwb_dat_i(iwb_dat_i),
.dwb_we_o(dwb_we_o),
.dwb_stb_o(dwb_stb_o),
.dwb_adr_o(dwb_adr_o),
.dwb_ack_i(dwb_ack_i),
+ .dwb_sel_o(dwb_sel_o),
+ .dwb_dat_i(dwb_dat_i),
+ .dwb_dat_o(dwb_dat_o),
+
+ .sys_int_i(sys_int_i),
+ .sys_exc_i(sys_exc_i) );
+
+endmodule // aeMB_core_BE
+
+// No longer needed byte-mangling
+/*
+ .iwb_dat_i({iwb_dat_i[7:0],
+ iwb_dat_i[15:8],
+ iwb_dat_i[23:16],
+ iwb_dat_i[31:24]}),
+
.dwb_sel_o({dwb_sel_o[0],
dwb_sel_o[1],
dwb_sel_o[2],
@@ -57,8 +70,4 @@
dwb_dat_o[15:8],
dwb_dat_o[23:16],
dwb_dat_o[31:24]}),
-
- .sys_int_i(sys_int_i),
- .sys_exc_i(sys_exc_i) );
-
-endmodule // aeMB_core_BE
+*/
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-04-30 18:02:39 UTC (rev 5193)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_decode.v,v 1.7 2007/04/27 04:23:17 sybreon Exp $
+ * $Id: aeMB_decode.v,v 1.8 2007/04/30 15:58:31 sybreon Exp $
*
* AEMB Instruction Decoder
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: aeMB_decode.v,v $
+ * Revision 1.8 2007/04/30 15:58:31 sybreon
+ * Fixed minor data hazard bug spotted by Matt Ettus.
+ *
* Revision 1.7 2007/04/27 04:23:17 sybreon
* Removed some unnecessary bubble control.
*
@@ -89,7 +92,7 @@
TODO: Modify this for block RAM based instruction cache.
*/
wire [31:0] wIREG;
- assign wIREG =
{iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]};
+ assign wIREG = iwb_dat_i;
wire [5:0] wOPC = wIREG[31:26];
wire [4:0] wRD = wIREG[25:21];
@@ -248,7 +251,7 @@
*/
reg [1:0] rMXSRC, rMXTGT, rMXALT, xMXSRC,xMXTGT,xMXALT;
- wire fRWE = (|rRD) & !(&rMXBRA);
+ wire fRWE = (|rRD) & !(&rMXBRA) & !(|rMXLDST);
always @(/*AUTOSENSE*/fBCC or fBRU or fRWE or rMXLDST or rRD
or wOPC or wRA or wRB) begin // frun
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-04-30 18:02:39 UTC (rev 5193)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.14 2007/04/27 15:15:49 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.15 2007/04/30 15:56:50 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -27,6 +27,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.15 2007/04/30 15:56:50 sybreon
+ * Removed byte acrobatics.
+ *
* Revision 1.14 2007/04/27 15:15:49 sybreon
* Fixed simulation bug.
*
@@ -143,8 +146,8 @@
wire [31:0] wDWBDAT;
reg [31:0] sDWBDAT;
reg [31:0] rDWBDAT;
- assign dwb_dat_o =
{rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
- assign wDWBDAT =
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
+ assign dwb_dat_o = rDWBDAT;
+ assign wDWBDAT = dwb_dat_i;
/**
RAM Based Register File
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-04-30 18:02:39 UTC (rev 5193)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/CVS/Entries
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,3 +1,3 @@
/utestbench.v/1.1/Fri Apr 13 13:02:34 2007//
-/testbench.v/1.3/Sat Apr 28 20:01:41 2007//
+/testbench.v/1.4/Mon Apr 30 17:31:54 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
2007-04-30 18:02:39 UTC (rev 5193)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/verilog/testbench.v
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,5 +1,5 @@
/*
- * $Id: testbench.v,v 1.3 2007/04/27 15:18:43 sybreon Exp $
+ * $Id: testbench.v,v 1.4 2007/04/30 15:56:50 sybreon Exp $
*
* AEMB Generic Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: testbench.v,v $
+ * Revision 1.4 2007/04/30 15:56:50 sybreon
+ * Removed byte acrobatics.
+ *
* Revision 1.3 2007/04/27 15:18:43 sybreon
* Minor updates as sw/c/aeMB_testbench.c got updated.
*
@@ -47,8 +50,8 @@
always #5 sys_clk_i = ~sys_clk_i;
initial begin
- $dumpfile("dump.vcd");
- $dumpvars(1,dut);
+ //$dumpfile("dump.vcd");
+ //$dumpvars(1,dut);
end
initial begin
@@ -85,9 +88,9 @@
wire [DSIZ-1:0] dwb_adr_o;
wire [31:0] dwb_dat_t;
- assign dwb_dat_i = ram[dadr];
- assign iwb_dat_i = ram[iadr];
- assign dwb_dat_t = ram[dwb_adr_o[DSIZ-1:2]];
+ assign
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]} = ram[dadr];
+ assign
{iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]} = ram[iadr];
+ assign {dwb_dat_t} = ram[dwb_adr_o[DSIZ-1:2]];
always @(posedge sys_clk_i) begin
iwb_ack_i <= #1 iwb_stb_o;
@@ -97,13 +100,13 @@
if (dwb_we_o & dwb_stb_o) begin
case (dwb_sel_o)
- 4'h1: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_t[31:8],dwb_dat_o[7:0]};
- 4'h2: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:16],dwb_dat_o[15:8],dwb_dat_t[7:0]};
- 4'h4: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:24],dwb_dat_o[23:16],dwb_dat_t[15:0]};
- 4'h8: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_o[31:24],dwb_dat_t[23:0]};
- 4'h3: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:16],dwb_dat_o[15:0]};
- 4'hC: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_o[31:16],dwb_dat_t[15:0]};
- 4'hF: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[31:0]};
+ 4'h1: ram[dwb_adr_o[DSIZ-1:2]] <= {dwb_dat_o[7:0],dwb_dat_t[23:0]};
+ 4'h2: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:24],dwb_dat_o[15:8],dwb_dat_t[15:0]};
+ 4'h4: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_t[7:0]};
+ 4'h8: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:8],dwb_dat_o[31:24]};
+ 4'h3: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_t[15:0]};
+ 4'hC: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_t[31:16],dwb_dat_o[23:16],dwb_dat_o[31:24]};
+ 4'hF: ram[dwb_adr_o[DSIZ-1:2]] <=
{dwb_dat_o[7:0],dwb_dat_o[15:8],dwb_dat_o[23:16],dwb_dat_o[31:24]};
endcase // case (dwb_sel_o)
end
end
@@ -111,7 +114,7 @@
integer i;
initial begin
for (i=0;i<65535;i=i+1) begin
- ram[i] <= 32'h0;
+ ram[i] <= $random;
end
#1 $readmemh("aeMB.rom",ram);
end
@@ -142,7 +145,7 @@
if (dwb_we_o & (dwb_dat_o == "PASS")) begin
$display("\tPASS");
end
- if (iwb_dat_i == 32'h000000b8) begin
+ if (iwb_dat_i == 32'hb8000000) begin
$display("\n\t*** PASSED ALL TESTS ***");
$finish;
end
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-04-30 18:02:39 UTC (rev 5193)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,2 +1,2 @@
D/c////
-/gccrom/1.3/Fri Apr 27 01:14:46 2007//
+/gccrom/1.4/Mon Apr 30 17:31:54 2007//
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-04-30 18:02:39 UTC (rev 5193)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,2 +1,2 @@
-/aeMB_testbench.c/1.5/Sat Apr 28 20:01:41 2007//
+/aeMB_testbench.c/1.6/Mon Apr 30 17:31:54 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-04-30 18:02:39 UTC (rev 5193)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_testbench.c,v 1.5 2007/04/27 15:17:59 sybreon Exp $
+ * $Id: aeMB_testbench.c,v 1.6 2007/04/30 15:57:10 sybreon Exp $
*
* AEMB Function Verification C Testbench
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -25,6 +25,9 @@
*
* HISTORY
* $Log: aeMB_testbench.c,v $
+ * Revision 1.6 2007/04/30 15:57:10 sybreon
+ * Removed byte acrobatics.
+ *
* Revision 1.5 2007/04/27 15:17:59 sybreon
* Added code documentation.
* Added new tests that test floating point, modulo arithmetic and
multiplication/division.
@@ -254,16 +257,16 @@
int* mpi = (int*)0xFFFFFFFF;
// Number of each test to run
- int max = 5;
+ int max = 3;
// Fibonacci Test
- if (fib_test(max) == -1) { *mpi = 0x4C494146; }
+ if (fib_test(max) == -1) { *mpi = 0x4641494C; }
// Euclid Test
- if (euclid_test(max) == -1) { *mpi = 0x4C494146; }
+ if (euclid_test(max) == -1) { *mpi = 0x4641494C; }
// Newton-Rhapson Test
- if (newton_test(max) == -1) { *mpi = 0x4C494146; }
+ if (newton_test(max) == -1) { *mpi = 0x4641494C; }
// ALL PASSED
return 0;
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
2007-04-30 18:02:39 UTC (rev 5193)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
2007-04-30 22:36:24 UTC (rev 5194)
@@ -1,6 +1,9 @@
#!/bin/sh
-# $Id: gccrom,v 1.3 2007/04/25 22:15:06 sybreon Exp $
+# $Id: gccrom,v 1.4 2007/04/30 15:57:31 sybreon Exp $
# $Log: gccrom,v $
+# Revision 1.4 2007/04/30 15:57:31 sybreon
+# Modified compilation sequence.
+#
# Revision 1.3 2007/04/25 22:15:06 sybreon
# Added support for 8-bit and 16-bit data types.
#
@@ -12,9 +15,9 @@
#
#mb-gcc -g -mxl-soft-div -mxl-soft-mul -msoft-float -mno-clearbss
-msmall-divides -mno-memcpy -mno-xl-gp-opt -o rom.o $@ && \
mb-gcc -g -mxl-soft-div -mxl-soft-mul -msoft-float -o rom.o $@ && \
+#mb-run -v rom.o 2> rom.run && \
mb-objcopy -O binary rom.o rom.bin && \
hexdump -v -e'1/4 "%.8X\n"' rom.bin > ../sim/aeMB.rom && \
mb-objdump -DSCs rom.o > rom.dump && \
rm rom.bin && \
-#mb-run -tv rom.o 2> rom.run && \
echo "ROM generated"
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- [Commit-gnuradio] r5194 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sim/verilog sim/verilog/CVS sw sw/CVS sw/c sw/c/CVS,
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