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[Commit-gnuradio] r5195 - in gnuradio/branches/developers/matt/u2f/top:
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5195 - in gnuradio/branches/developers/matt/u2f/top: u2_basic u2_fpga u2_sim |
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Date: |
Mon, 30 Apr 2007 16:37:44 -0600 (MDT) |
Author: matt
Date: 2007-04-30 16:37:44 -0600 (Mon, 30 Apr 2007)
New Revision: 5195
Modified:
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
gnuradio/branches/developers/matt/u2f/top/u2_sim/
gnuradio/branches/developers/matt/u2f/top/u2_sim/cpld_model.v
gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
Log:
refactored all the SPI stuff so we can use a single spi core
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-30 22:36:24 UTC (rev 5194)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-30 22:37:44 UTC (rev 5195)
@@ -122,43 +122,19 @@
// Generic SPI
output sclk,
+ output mosi,
+ input miso,
output sen_clk,
output sen_dac,
- output sdi,
- input sdo,
+ output sen_tx_db,
+ output sen_tx_adc,
+ output sen_tx_dac,
+ output sen_rx_db,
+ output sen_rx_adc,
+ output sen_rx_dac,
- // TX DBoard
- input sen_tx_db,
- input sclk_tx_db,
- input sdo_tx_db,
- input sdi_tx_db,
-
- input sen_tx_adc,
- input sclk_tx_adc,
- input sdo_tx_adc,
- input sdi_tx_adc,
-
- input sen_tx_dac,
- input sclk_tx_dac,
- input sdi_tx_dac,
-
+ // GPIO to DBoards
inout [15:0] io_tx,
-
- // RX DBoard
- input sen_rx_db,
- input sclk_rx_db,
- input sdo_rx_db,
- input sdi_rx_db,
-
- input sen_rx_adc,
- input sclk_rx_adc,
- input sdo_rx_adc,
- input sdi_rx_adc,
-
- input sen_rx_dac,
- input sclk_rx_dac,
- input sdi_rx_dac,
-
inout [15:0] io_rx
);
@@ -169,7 +145,7 @@
assign
debug={{ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,processor_rst,wb_rst,dsp_rst},
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
{sysctrl_dbg},
- {2'b0, clk_status, sen_dac, sen_clk, sclk, sdi, sdo}};
+ {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
assign debug_clk[0] = aux_clk;
assign debug_clk[1] = clk_fpga;
@@ -252,14 +228,20 @@
.iwb_adr_i(iwb_adr),.iwb_dat_o(iwb_dat),.iwb_stb_i(iwb_stb),.iwb_ack_o(iwb_ack),
.dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
.dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel));
+
+ assign s0_err = 1'b0;
+ assign s0_rty = 1'b0;
// SPI -- Slave #1
spi_top shared_spi
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),.wb_dat_o(s1_dat_i),
.wb_sel_i(s1_sel),.wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_cyc_i(s1_cyc),.wb_ack_o(s1_ack),
.wb_err_o(s1_err),.wb_int_o(s1_int),
-
.ss_pad_o({sen_dac,sen_clk}),.sclk_pad_o(sclk),.mosi_pad_o(sdi),.miso_pad_i(sdo)
);
+
.ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+ .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+ assign s1_rty = 1'b0;
+
// I2C -- Slave #2
i2c_master_top #(.ARST_LVL(1))
i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0),
@@ -269,32 +251,36 @@
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+ assign s2_err = 1'b0;
+ assign s2_rty = 1'b0;
+
// GPIOs -- Slave #3
wire s3_ack_a, s3_ack_b, s3_ack_c, s3_ack_d;
- //assign s3_ack = 1'b0;
-
assign s3_ack = s3_ack_a | s3_ack_b | s3_ack_c | s3_ack_d;
- simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(wb_rst),
+ simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[0]),.adr_i(s3_adr[2]),.we_i(s3_we),
.dat_i(s3_dat_o[7:0]),.dat_o(s3_dat_i[7:0]),.ack_o(s3_ack_a),
.gpio(io_tx[7:0]) );
- simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(wb_rst),
+ simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[1]),.adr_i(s3_adr[2]),.we_i(s3_we),
.dat_i(s3_dat_o[15:8]),.dat_o(s3_dat_i[15:8]),.ack_o(s3_ack_b),
.gpio(io_tx[15:8]) );
- simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(wb_rst),
+ simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[2]),.adr_i(s3_adr[2]),.we_i(s3_we),
.dat_i(s3_dat_o[23:16]),.dat_o(s3_dat_i[23:16]),.ack_o(s3_ack_c),
.gpio(io_rx[7:0]) );
- simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(wb_rst),
+ simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[3]),.adr_i(s3_adr[2]),.we_i(s3_we),
.dat_i(s3_dat_o[31:24]),.dat_o(s3_dat_i[31:24]),.ack_o(s3_ack_d),
.gpio(io_rx[15:8]) );
-
+
+ assign s3_err = 1'b0;
+ assign s3_rty = 1'b0;
+
//
////////////////////////////////////////////////////////////////////////////////////
// Output control lines, SLAVE #4
// organized in 4 8-bit segments -- clock, serdes, adc, led+misc
@@ -308,7 +294,10 @@
(.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s4_dat_o),.wb_dat_o(s4_dat_i),
.wb_we_i(s4_we),.wb_sel_i(s4_sel),.wb_stb_i(s4_stb),.wb_ack_o(s4_ack),.wb_cyc_i(s4_cyc),
.port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) );
-
+
+ assign s4_err = 1'b0;
+ assign s4_rty = 1'b0;
+
//////////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Shared Bus
wb_conbus_top #(.s0_addr_w(4),.s0_addr(4'h0),.s1_addr_w(4),.s1_addr(4'h1),
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-04-30 22:36:24 UTC (rev 5194)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-04-30 22:37:44 UTC (rev 5195)
@@ -123,36 +123,36 @@
input sdo,
// TX DBoard
- input sen_tx_db,
- input sclk_tx_db,
+ output sen_tx_db,
+ output sclk_tx_db,
input sdo_tx_db,
- input sdi_tx_db,
+ output sdi_tx_db,
- input sen_tx_adc,
- input sclk_tx_adc,
+ output sen_tx_adc,
+ output sclk_tx_adc,
input sdo_tx_adc,
- input sdi_tx_adc,
+ output sdi_tx_adc,
- input sen_tx_dac,
- input sclk_tx_dac,
- input sdi_tx_dac,
+ output sen_tx_dac,
+ output sclk_tx_dac,
+ output sdi_tx_dac,
inout [15:0] io_tx,
// RX DBoard
- input sen_rx_db,
- input sclk_rx_db,
+ output sen_rx_db,
+ output sclk_rx_db,
input sdo_rx_db,
- input sdi_rx_db,
+ output sdi_rx_db,
- input sen_rx_adc,
- input sclk_rx_adc,
+ output sen_rx_adc,
+ output sclk_rx_adc,
input sdo_rx_adc,
- input sdi_rx_adc,
+ output sdi_rx_adc,
- input sen_rx_dac,
- input sclk_rx_dac,
- input sdi_rx_dac,
+ output sen_rx_dac,
+ output sclk_rx_dac,
+ output sdi_rx_dac,
inout [15:0] io_rx
);
@@ -185,6 +185,20 @@
wire aux_clk = RAM_CE1n; // FIXME Hacked on with Blue Wire
wire cpld_detached = RAM_A[14]; // FIXME Hacked on with Blue Wire
+ // SPI
+ wire miso, mosi, sclk_int;
+ assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+ assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+
+ assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
+ (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+ (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
u2_basic u2_basic(.clk_fpga (clk_fpga),
.aux_clk (aux_clk),
.clk_to_mac (clk_to_mac),
@@ -249,34 +263,18 @@
.clk_sel (clk_sel[1:0]),
.clk_func (clk_func),
.clk_status (clk_status),
- .sclk (sclk),
+ .sclk (sclk_int),
+ .mosi (mosi),
+ .miso (miso),
.sen_clk (sen_clk),
.sen_dac (sen_dac),
- .sdi (sdi),
- .sdo (sdo),
.sen_tx_db (sen_tx_db),
- .sclk_tx_db (sclk_tx_db),
- .sdo_tx_db (sdo_tx_db),
- .sdi_tx_db (sdi_tx_db),
.sen_tx_adc (sen_tx_adc),
- .sclk_tx_adc (sclk_tx_adc),
- .sdo_tx_adc (sdo_tx_adc),
- .sdi_tx_adc (sdi_tx_adc),
.sen_tx_dac (sen_tx_dac),
- .sclk_tx_dac (sclk_tx_dac),
- .sdi_tx_dac (sdi_tx_dac),
- .io_tx (io_tx[15:0]),
.sen_rx_db (sen_rx_db),
- .sclk_rx_db (sclk_rx_db),
- .sdo_rx_db (sdo_rx_db),
- .sdi_rx_db (sdi_rx_db),
.sen_rx_adc (sen_rx_adc),
- .sclk_rx_adc (sclk_rx_adc),
- .sdo_rx_adc (sdo_rx_adc),
- .sdi_rx_adc (sdi_rx_adc),
.sen_rx_dac (sen_rx_dac),
- .sclk_rx_dac (sclk_rx_dac),
- .sdi_rx_dac (sdi_rx_dac),
+ .io_tx (io_tx[15:0]),
.io_rx (io_rx[15:0]));
endmodule // u2_fpga_top
Property changes on: gnuradio/branches/developers/matt/u2f/top/u2_sim
___________________________________________________________________
Name: svn:ignore
+ *.vcd
Modified: gnuradio/branches/developers/matt/u2f/top/u2_sim/cpld_model.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim/cpld_model.v
2007-04-30 22:36:24 UTC (rev 5194)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim/cpld_model.v
2007-04-30 22:37:44 UTC (rev 5195)
@@ -1,5 +1,5 @@
-module cpld_model //#(parameter romfile="flash.rom")
+module cpld_model
(input aux_clk, input start, input mode, input done,
output dout, output sclk, output detached);
Modified: gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
2007-04-30 22:36:24 UTC (rev 5194)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim/u2_sim_top.v
2007-04-30 22:37:44 UTC (rev 5195)
@@ -1,17 +1,9 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
-// Module Name: safe_bringup
-//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-//
-//////////////////////////////////////////////////////////////////////////////////
// Nearly everything is an input
module u2_sim_top();
-
// Misc, debug
wire led1;
wire led2;
@@ -91,7 +83,6 @@
wire [15:0] dac_a;
wire [15:0] dac_b;
-
// I2C
wire SCL;
wire SDA;
@@ -108,44 +99,18 @@
wire pps_in;
// Generic SPI
- wire sclk;
+ wire sclk, mosi, miso;
wire sen_clk;
wire sen_dac;
- wire sdi;
- wire sdo;
-
- // TX DBoard
wire sen_tx_db;
- wire sclk_tx_db;
- wire sdo_tx_db;
- wire sdi_tx_db;
-
wire sen_tx_adc;
- wire sclk_tx_adc;
- wire sdo_tx_adc;
- wire sdi_tx_adc;
-
wire sen_tx_dac;
- wire sclk_tx_dac;
- wire sdi_tx_dac;
-
- wire [15:0] io_tx;
-
- // RX DBoard
wire sen_rx_db;
- wire sclk_rx_db;
- wire sdo_rx_db;
- wire sdi_rx_db;
-
wire sen_rx_adc;
- wire sclk_rx_adc;
- wire sdo_rx_adc;
- wire sdi_rx_adc;
-
wire sen_rx_dac;
- wire sclk_rx_dac;
- wire sdi_rx_dac;
+ // GPIO to DBoards
+ wire [15:0] io_tx;
wire [15:0] io_rx;
wire wb_clk, wb_rst;
@@ -167,46 +132,20 @@
initial #10000000 $finish;
- cpld_model #(.romfile(""))
+ cpld_model
cpld_model
(.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
.dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
- u2_basic u2_basic(/*AUTOINST*/
- // Outputs
+ u2_basic u2_basic(.clk_fpga (clk_fpga),
+ .aux_clk (aux_clk),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
.led1 (led1),
.led2 (led2),
.debug (debug[31:0]),
.debug_clk (debug_clk[1:0]),
- .exp_pps_out (exp_pps_out),
- .ser_enable (ser_enable),
- .ser_prbsen (ser_prbsen),
- .ser_loopen (ser_loopen),
- .ser_rx_en (ser_rx_en),
- .cpld_start (cpld_start),
- .cpld_mode (cpld_mode),
- .cpld_done (cpld_done),
- .adc_oen_a (adc_oen_a),
- .adc_pdn_a (adc_pdn_a),
- .adc_oen_b (adc_oen_b),
- .adc_pdn_b (adc_pdn_b),
- .dac_a (dac_a[15:0]),
- .dac_b (dac_b[15:0]),
- .scl_pad_o (scl_pad_o),
- .scl_pad_oen_o (scl_pad_oen_o),
- .sda_pad_o (sda_pad_o),
- .sda_pad_oen_o (sda_pad_oen_o),
- .clk_en (clk_en[1:0]),
- .clk_sel (clk_sel[1:0]),
- .sclk (sclk),
- .sen_clk (sen_clk),
- .sen_dac (sen_dac),
- .sdi (sdi),
- // Inputs
- .clk_fpga (clk_fpga),
- .aux_clk (aux_clk),
- .clk_to_mac (clk_to_mac),
- .pps_in (pps_in),
.exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
.GMII_COL (GMII_COL),
.GMII_CRS (GMII_CRS),
.GMII_TXD (GMII_TXD[7:0]),
@@ -223,6 +162,10 @@
.PHY_INTn (PHY_INTn),
.PHY_RESETn (PHY_RESETn),
.PHY_CLK (PHY_CLK),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
.ser_tx_clk (ser_tx_clk),
.ser_t (ser_t[15:0]),
.ser_tklsb (ser_tklsb),
@@ -231,43 +174,45 @@
.ser_r (ser_r[15:0]),
.ser_rklsb (ser_rklsb),
.ser_rkmsb (ser_rkmsb),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
.cpld_din (cpld_din),
.cpld_clk (cpld_clk),
.cpld_detached (cpld_detached),
.adc_a (adc_a[13:0]),
.adc_ovf_a (adc_ovf_a),
+ .adc_oen_a (adc_oen_a),
+ .adc_pdn_a (adc_pdn_a),
.adc_b (adc_b[13:0]),
.adc_ovf_b (adc_ovf_b),
+ .adc_oen_b (adc_oen_b),
+ .adc_pdn_b (adc_pdn_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
.scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
.sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
.clk_func (clk_func),
.clk_status (clk_status),
- .sdo (sdo),
+ .sclk (sclk),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
.sen_tx_db (sen_tx_db),
- .sclk_tx_db (sclk_tx_db),
- .sdo_tx_db (sdo_tx_db),
- .sdi_tx_db (sdi_tx_db),
.sen_tx_adc (sen_tx_adc),
- .sclk_tx_adc (sclk_tx_adc),
- .sdo_tx_adc (sdo_tx_adc),
- .sdi_tx_adc (sdi_tx_adc),
.sen_tx_dac (sen_tx_dac),
- .sclk_tx_dac (sclk_tx_dac),
- .sdi_tx_dac (sdi_tx_dac),
- .io_tx (io_tx[15:0]),
.sen_rx_db (sen_rx_db),
- .sclk_rx_db (sclk_rx_db),
- .sdo_rx_db (sdo_rx_db),
- .sdi_rx_db (sdi_rx_db),
.sen_rx_adc (sen_rx_adc),
- .sclk_rx_adc (sclk_rx_adc),
- .sdo_rx_adc (sdo_rx_adc),
- .sdi_rx_adc (sdi_rx_adc),
.sen_rx_dac (sen_rx_dac),
- .sclk_rx_dac (sclk_rx_dac),
- .sdi_rx_dac (sdi_rx_dac),
+ .io_tx (io_tx[15:0]),
.io_rx (io_rx[15:0]));
-
endmodule // u2_sim_top
// Local Variables:
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- [Commit-gnuradio] r5195 - in gnuradio/branches/developers/matt/u2f/top: u2_basic u2_fpga u2_sim,
matt <=