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[Commit-gnuradio] r5735 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5735 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations |
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Date: |
Thu, 7 Jun 2007 12:27:49 -0600 (MDT) |
Author: thottelt
Date: 2007-06-07 12:27:48 -0600 (Thu, 07 Jun 2007)
New Revision: 5735
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
fixed delay cell, sine seems right, swapped i/q samples
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-07 16:11:48 UTC (rev 5734)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-07 18:27:48 UTC (rev 5735)
@@ -122,7 +122,7 @@
tx_empty <= 1 ;
// Let's send it
- /*if ((timestamp < adc_time + `JITTER
+ if ((timestamp < adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
reader_state <= `WAITSTROBE;
@@ -136,9 +136,9 @@
begin
reader_state <= `DISCARD;
skip <= 1;
- end*/
+ end
- reader_state <= `WAITSTROBE;
+ //reader_state <= `WAITSTROBE;
end
// Wait for the transmit chain to be ready
@@ -170,15 +170,15 @@
case(samples_format)
`QI16:
begin
- tx_q <= fifodata[15:0];
- tx_i <= fifodata[31:16];
+ tx_i <= fifodata[15:0];
+ tx_q <= fifodata[31:16];
end
// Assume 16 bits complex samples by default
default:
begin
- tx_q <= fifodata[15:0];
- tx_i <= fifodata[31:16];
+ tx_i <= fifodata[15:0];
+ tx_q <= fifodata[31:16];
end
endcase
end
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-07 16:11:48 UTC (rev 5734)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-07 18:27:48 UTC (rev 5735)
@@ -142,11 +142,29 @@
WR_tx <= WR_1 & ~WR_2;
end
+ reg [31:0] usbdata_final;
+ reg WR_final;
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ WR_final <= 0;
+ else
+ begin
+ WR_final <= WR_tx;
+ if (WR_tx)
+ usbdata_final <= usbdata_tx;
+ end
+ end
+
+
+
+
/* Parse header and forward to ram */
reg [3:0]reader_state;
reg [4:0]channel ;
reg [9:0]pkt_length ;
- reg [9:0]read_length ;
+ reg [9:0]read_length ;
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
@@ -166,30 +184,32 @@
else
case (reader_state)
IDLE: begin
- if (WR_tx)
+ if (WR_final)
reader_state <= HEADER;
end
HEADER: begin
- channel <= (usbdata_tx[20:16]) ;
+ //channel <= (usbdata_tx[20:16]) ;
+ channel <= 0 ;
pkt_length <= usbdata_tx[8:0] + 9'd8;
read_length <= 10'd4 ;
- WR_channel[usbdata_tx[20:16]] <= 1;
- ram_data <= usbdata_tx;
+ //WR_channel[usbdata_tx[20:16]] <= 1;
+ WR_channel[0] <= 1;
+ ram_data <= usbdata_final;
reader_state <= WAIT;
end
FORWARD_HEADER: begin
WR_channel[channel] <= 1;
- ram_data <= usbdata_tx;
+ ram_data <= usbdata_final;
reader_state <= WAIT;
end
WAIT: begin
WR_channel[channel] <= 0;
- if (WR_tx)
+ if (WR_final)
begin
reader_state <= FORWARD;
end
@@ -197,7 +217,7 @@
FORWARD: begin
WR_channel[channel] <= 1;
- ram_data <= usbdata_tx;
+ ram_data <= usbdata_final;
read_length <= read_length + 9'd4;
reader_state <= WAIT2;
@@ -209,7 +229,7 @@
if (read_length == 512)
reader_state <= IDLE;
- if (WR_tx)
+ if (WR_final)
reader_state <= FORWARD;
end
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-07 16:11:48 UTC (rev 5734)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-06-07 18:27:48 UTC (rev 5735)
@@ -377,8 +377,6 @@
set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_writer.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-07
16:11:48 UTC (rev 5734)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-07
18:27:48 UTC (rev 5735)
@@ -269,7 +269,7 @@
Project_File_11 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181158584 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181232994 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181234493 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = ./chan_fifo_readers_test.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181074819 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = ../inband/usrp/fpga/megacells/fifo_1k.v
@@ -319,6 +319,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v 0 0} {Z:/wc/simulations/fake_fx2.v
0 0} {Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/strobe_gen.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_writer.v 0 1}
+EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 1}
{Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v 0 0} {Z:/wc/simulations/fake_fx2.v
0 0} {Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/strobe_gen.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
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