[Commit-gnuradio] r5736 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations

[thottelt]

Author: thottelt
Date: 2007-06-07 20:12:21 -0600 (Thu, 07 Jun 2007)
New Revision: 5736

Modified:
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
   gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v
   gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
everything works like in a dream, what a beautiful sine wave. Channel, 
timestamp and payload read correctly but code needs cleaned.

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
        2007-06-07 18:27:48 UTC (rev 5735)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
        2007-06-08 02:12:21 UTC (rev 5736)
@@ -100,8 +100,8 @@
                    else if (fifodata[27] == 1)
                        burst <= 0;
                        
-                   //payload_len <= fifodata[8:0] ;
-                                  payload_len <= 9'd504 ;
+                   payload_len <= fifodata[8:0] ;
+                                  //payload_len <= 9'd504 ;
                    read_len <= 0;
                         
                    rdreq <= 0;

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v 
    2007-06-07 18:27:48 UTC (rev 5735)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/channel_ram.v 
    2007-06-08 02:12:21 UTC (rev 5736)
@@ -61,7 +61,7 @@
                else if (wr_done_int) 
                        which_ram_wr <= which_ram_wr + 2'd1;
        
-       assign have_space = (nb_packets < 4);
+       assign have_space = (nb_packets < 3);
                
        // Reader side
        always @(posedge txclk)  dataout0 <= ram0[rd_addr];

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
 2007-06-07 18:27:48 UTC (rev 5735)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
 2007-06-08 02:12:21 UTC (rev 5736)
@@ -189,13 +189,13 @@
               end
               
               HEADER: begin
-                 //channel <= (usbdata_tx[20:16]) ;
-                 channel <= 0 ;
-                 pkt_length <= usbdata_tx[8:0] + 9'd8;
+                 channel <= (usbdata_final[20:16]) ;
+                 //channel <= 0 ;
+                 pkt_length <= usbdata_final[8:0] + 9'd8;
                  read_length <= 10'd4 ;
                  
-                 //WR_channel[usbdata_tx[20:16]] <= 1;
-                 WR_channel[0] <= 1;
+                 WR_channel[usbdata_final[20:16]] <= 1;
+                 //WR_channel[0] <= 1;
                  ram_data <= usbdata_final;
                  reader_state <= WAIT;
               end

Modified: gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v   
2007-06-07 18:27:48 UTC (rev 5735)
+++ gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v   
2007-06-08 02:12:21 UTC (rev 5736)
@@ -23,13 +23,13 @@
     begin
         if (tx_empty == 0)
           begin
-            if (tx_q != counter)
+            if (tx_i != counter)
             begin
                 ok = 0 ;
                 $display("Q samples do not match");
                 //$finish;
             end
-            if (tx_i != counter + 1)
+            if (tx_q != counter + 1)
             begin
                 ok = 0 ;
                 $display("I samples do not match");

Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-06-07 
18:27:48 UTC (rev 5735)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-06-08 
02:12:21 UTC (rev 5736)
@@ -249,11 +249,11 @@
 Project_File_1 = ./usb_fifo_writer_test.v
 Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181165989 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
14 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_2 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181184228 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
21 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181267786 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_3 = Z:/wc/simulations/data_packet_fifo_test.v
 Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_4 = Z:/wc/simulations/fake_tx_chain.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180840688 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
17 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181267665 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_5 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
 Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_6 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
@@ -263,13 +263,13 @@
 Project_File_8 = ./fake_fx2.v
 Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181183422 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
11 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_9 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181186488 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181243950 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_10 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
 Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180995228 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8 
dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_11 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
 Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181158584 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181234493 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181267510 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
13 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_13 = ./chan_fifo_readers_test.v
 Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181074819 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1 
dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_14 = ../inband/usrp/fpga/megacells/fifo_1k.v
@@ -319,6 +319,6 @@
 XML_CustomDoubleClick = 
 LOGFILE_DoubleClick = Edit
 LOGFILE_CustomDoubleClick = 
-EditorState = {tabbed horizontal 1} 
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 1} 
{Z:/wc/simulations/tx_buffer_test.v 0 0} 
{Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v 0 0} {Z:/wc/simulations/fake_fx2.v 
0 0} {Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0} 
{Z:/wc/inband/usrp/fpga/sdr_lib/strobe_gen.v 0 0} 
{Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v 0 0}
+EditorState = {tabbed horizontal 0}
 Project_Major_Version = 6
 Project_Minor_Version = 1