[Commit-gnuradio] r7376 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-01-07 18:07:08 -0700 (Mon, 07 Jan 2008)
New Revision: 7376

Added:
   usrp2/trunk/fpga/control_lib/wb_ram_block.v
   usrp2/trunk/fpga/control_lib/wb_ram_dist.v
Log:
basic single-ported rams.  We can use these for data space for the processor.


Added: usrp2/trunk/fpga/control_lib/wb_ram_block.v
===================================================================
--- usrp2/trunk/fpga/control_lib/wb_ram_block.v                         (rev 0)
+++ usrp2/trunk/fpga/control_lib/wb_ram_block.v 2008-01-08 01:07:08 UTC (rev 
7376)
@@ -0,0 +1,36 @@
+
+
+// Since this is a block ram, there are no byte-selects and there is a 1-cycle 
read latency
+//   These have to be a multiple of 512 lines (2K) long
+
+module wb_ram_block
+  #(parameter AWIDTH=9)
+    (input clk_i,
+     input stb_i,
+     input we_i,
+     input [AWIDTH-1:0] adr_i,
+     input [31:0] dat_i,
+     output reg [31:0] dat_o,
+     output ack_o);
+
+   reg [31:0] distram [0:1<<(AWIDTH-1)];
+
+   always @(posedge clk_i)
+     begin
+       if(stb_i & we_i)
+         distram[adr_i] <= dat_i;
+       dat_o <= distram[adr_i];
+     end
+
+   reg stb_d1, ack_d1;
+   always @(posedge clk_i)
+     stb_d1 <= stb_i;
+   
+   always @(posedge clk_i)
+     ack_d1 <= ack_o;
+   
+   assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1));
+endmodule // wb_ram_block
+
+
+    

Added: usrp2/trunk/fpga/control_lib/wb_ram_dist.v
===================================================================
--- usrp2/trunk/fpga/control_lib/wb_ram_dist.v                          (rev 0)
+++ usrp2/trunk/fpga/control_lib/wb_ram_dist.v  2008-01-08 01:07:08 UTC (rev 
7376)
@@ -0,0 +1,33 @@
+
+
+module wb_ram_dist
+  #(parameter AWIDTH=8)
+    (input clk_i,
+     input stb_i,
+     input we_i,
+     input [AWIDTH-1:0] adr_i,
+     input [31:0] dat_i,
+     input [3:0] sel_i,
+     output [31:0] dat_o,
+     output ack_o);
+
+   reg [31:0] distram [0:1<<(AWIDTH-1)];
+
+   always @(posedge clk_i)
+     begin
+       if(stb_i & we_i & sel_i[3])
+         distram[adr_i][31:24] <= dat_i[31:24];
+       if(stb_i & we_i & sel_i[2])
+         distram[adr_i][24:16] <= dat_i[24:16];
+       if(stb_i & we_i & sel_i[1])
+         distram[adr_i][15:8] <= dat_i[15:8];
+       if(stb_i & we_i & sel_i[0])
+         distram[adr_i][7:0] <= dat_i[7:0];
+     end // always @ (posedge clk_i)
+
+   assign dat_o = distram[adr_i];
+   assign ack_o = stb_i;
+
+endmodule // wb_ram_dist
+
+