[Commit-gnuradio] r7377 - usrp2/trunk/fpga/eth

[matt]

Author: matt
Date: 2008-01-07 19:18:37 -0700 (Mon, 07 Jan 2008)
New Revision: 7377

Added:
   usrp2/trunk/fpga/eth/header_ram.v
   usrp2/trunk/fpga/eth/rx_prot_engine.v
   usrp2/trunk/fpga/eth/tx_prot_engine.v
Log:
first cut at a protocol processor for our transport protocol


Added: usrp2/trunk/fpga/eth/header_ram.v
===================================================================
--- usrp2/trunk/fpga/eth/header_ram.v                           (rev 0)
+++ usrp2/trunk/fpga/eth/header_ram.v   2008-01-08 02:18:37 UTC (rev 7377)
@@ -0,0 +1,24 @@
+
+module header_ram
+  #(parameter REGNUM=0,
+    parameter WIDTH=32)
+    (input clk,
+     input set_stb,
+     input [7:0] set_addr,
+     input [31:0] set_data,
+     
+     input [3:0] addr,
+     output [31:0] q 
+     );
+   
+   reg [WIDTH-1:0] mini_ram[0:15];
+   wire           write_to_ram = (set_stb & (set_addr[7:4]==REGNUM));
+   wire [3:0]     ram_addr = write_to_ram ? set_addr[3:0] : addr;
+                  
+   always @(posedge clk)
+     if(write_to_ram)
+       mini_ram[ram_addr] <= set_data;
+
+   assign         q = mini_ram[ram_addr];
+
+endmodule // header_ram

Added: usrp2/trunk/fpga/eth/rx_prot_engine.v
===================================================================
--- usrp2/trunk/fpga/eth/rx_prot_engine.v                               (rev 0)
+++ usrp2/trunk/fpga/eth/rx_prot_engine.v       2008-01-08 02:18:37 UTC (rev 
7377)
@@ -0,0 +1,93 @@
+
+module rx_prot_engine
+  #(parameter FIFO_SIZE=11)
+    (input clk, input rst,
+     
+     input Rx_mac_ra,
+     output Rx_mac_rd,
+     input [31:0] Rx_mac_data,
+     input [1:0] Rx_mac_BE,
+     input Rx_mac_pa,
+     input Rx_mac_sop,
+     input Rx_mac_eop,
+     input Rx_mac_err,
+     
+     output [31:0] wr_dat_o,
+     output wr_write_o,
+     output wr_done_o,
+     output wr_error_o,
+     input wr_ready_i,
+     input wr_full_i,
+
+     input set_stb,
+     input [7:0] set_addr,
+     input [31:0] set_data,
+     
+     output [15:0] rx_fifo_status,
+     output [7:0] rx_seqnum,
+     output [7:0] rx_channel,
+     output [7:0] flags
+     );
+
+   wire          read, write, full, empty;
+   wire          eop_i, err_i, eop_o, err_o;
+   wire [31:0]           dat_i, dat_o;
+   reg                   xfer_active;
+
+   wire [3:0]    hdr_adr;
+   wire [31:0]           hdr_dat;
+   header_ram #(.REGNUM(0),.WIDTH(32)) rx_header_ram
+     (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .addr(hdr_adr),.q(hdr_dat));
+
+   // Buffer interface side
+   always @(posedge clk)
+     if(rst)
+       xfer_active <= 0;
+     else if(wr_ready_i & ~empty)
+       xfer_active <= 1;
+     else if(eop_o | err_o | wr_full_i)
+       xfer_active <= 0;
+
+   assign wr_done_o = eop_o;
+   assign wr_error_o = err_o;
+   assign wr_dat_o = dat_o;
+   assign wr_write_o = xfer_active & ~empty;
+   assign read = wr_write_o;
+
+   // FIFO in the middle
+   cascadefifo2 #(.WIDTH(34),.SIZE(11)) rx_prot_fifo
+     (.clk(clk),.rst(rst),
+      .datain({eop_i,err_i,dat_i}),.write(write),.full(full),
+      .dataout({eop_o,err_o,dat_o}),.read(read),.empty(empty),
+      .clear(0),.fifo_space(rx_fifo_status));
+
+   // MAC side
+   localparam ETH_TYPE = 16'hBEEF;
+   
+   reg [2:0] prot_state;
+   localparam PROT_IDLE = 0;
+   localparam PROT_HDR1 = 1;
+   localparam PROT_HDR2 = 2;
+   localparam PROT_HDR3 = 3;
+   localparam PROT_HDR4 = 4;
+   localparam PROT_PKT = 5;
+
+   // Things to control: eop_i, err_i, dat_i, write, Rx_mac_rd
+   // Inputs to SM: Rx_mac_sop_i, Rx_mac_eop_i, Rx_mac_ra, Rx_mac_pa, 
+   //                Rx_mac_BE, Rx_mac_err, full
+   always @(posedge clk)
+     if(rst)
+       prot_state <= PROT_IDLE;
+     else
+       case(prot_state)
+        PROT_IDLE : ;
+        PROT_HDR1 : ;
+        PROT_HDR2 : ;
+        PROT_HDR3 : ;
+        PROT_HDR4 : ;
+        PROT_PKT : ;
+       endcase // case(prot_state)
+   
+   // Error cases -- Rx_mac_error, BE != 0, bad_seqno
+endmodule // rx_prot_engine

Added: usrp2/trunk/fpga/eth/tx_prot_engine.v
===================================================================
--- usrp2/trunk/fpga/eth/tx_prot_engine.v                               (rev 0)
+++ usrp2/trunk/fpga/eth/tx_prot_engine.v       2008-01-08 02:18:37 UTC (rev 
7377)
@@ -0,0 +1,128 @@
+
+module tx_prot_engine
+  (input clk, input rst,
+   
+   // To MAC
+   input Tx_mac_wa,
+   output Tx_mac_wr,
+   output [31:0] Tx_mac_data,
+   output [1:0] Tx_mac_BE,
+   output Tx_mac_sop,
+   output Tx_mac_eop,
+
+   // To buffer interface
+   input [31:0] rd_dat_i,
+   output rd_read_o,
+   output rd_done_o,
+   output rd_error_o,
+   input rd_sop_i,
+   input rd_eop_i,
+
+   // To control
+   input set_stb,
+   input [7:0] set_addr,
+   input [31:0] set_data,
+
+   // Protocol Stuff
+   input [7:0] channel,
+   input [7:0] rx_seqnum,
+   input [15:0] rx_fifo_status
+   );
+
+   wire [3:0]  hdr_adr;
+   wire [31:0]         hdr_dat;
+   header_ram #(.REGNUM(0),.WIDTH(32)) tx_header_ram
+     (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .addr(hdr_adr),.q(hdr_dat));
+   
+   // Might as well use a shortfifo here since they are basically free
+   wire  empty, full, sfifo_write, sfifo_read;
+   wire [33:0] sfifo_in, sfifo_out;
+   
+   shortfifo #(.WIDTH(34)) txmac_sfifo
+     (.clk(clk),.rst(rst),.clear(0),
+      .datain(sfifo_in),.write(sfifo_write),.full(full),
+      .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
+
+   // MAC side signals
+   //  We are allowed to do one more write after we are told the FIFO is full
+   //  This allows us to register the _wa signal and speed up timing.
+
+   reg                tx_seqnum;
+   reg                tx_mac_wa_d1;
+   always @(posedge clk)
+     tx_mac_wa_d1 <= Tx_mac_wa;
+
+   reg [2:0]   prot_state;
+   localparam  PROT_IDLE = 0;
+   localparam  PROT_HDR1 = 1;
+   localparam  PROT_HDR2 = 2;
+   localparam  PROT_HDR3 = 3;
+   localparam  PROT_HDR4 = 4;
+   localparam  PROT_PKT  = 5;
+   localparam  PROT_TRAIL = 6;
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+         tx_seqnum <= 0;
+         prot_state <= PROT_IDLE;
+       end
+     else
+       if(tx_mac_wa_d1)
+        case(prot_state)
+          PROT_IDLE :
+            if(~empty)
+              prot_state <= PROT_HDR1;
+          PROT_HDR1 :
+            prot_state <= PROT_HDR2;
+          PROT_HDR2 :
+            prot_state <= PROT_HDR3;
+          PROT_HDR3 :
+            prot_state <= PROT_HDR4;
+          PROT_HDR4 :
+            prot_state <= PROT_PKT;
+          PROT_PKT :
+            if(sfifo_out[32] & ~empty)
+              prot_state <= PROT_TRAIL;
+          PROT_TRAIL :
+            begin
+               prot_state <= PROT_IDLE;
+               tx_seqnum <= tx_seqnum + 1;
+            end
+          default :
+            prot_state <= PROT_IDLE;
+        endcase // case(prot_state)
+
+   localparam  ETH_TYPE = 16'hBEEF;
+   assign      Tx_mac_data = (prot_state == PROT_PKT) ? sfifo_out[31:0] : 
+                            (prot_state == PROT_HDR4) ? 
{ETH_TYPE,channel,tx_seqnum} :
+                            (prot_state == PROT_TRAIL) ? 
{rx_fifo_status,8'b0,rx_seqnum} : 
+                            hdr_dat;
+
+   assign      hdr_adr = {1'b0,prot_state};
+                             
+   assign      sfifo_read = (prot_state == PROT_PKT) & ~empty & tx_mac_wa_d1;
+   assign      Tx_mac_wr = tx_mac_wa_d1 & (prot_state != PROT_IDLE) & 
((prot_state != PROT_PKT)|~empty);
+   assign      Tx_mac_BE = 0;  // Since we only deal with packets that are 
multiples of 32 bits long
+   assign      Tx_mac_sop = (prot_state == PROT_HDR1); // sfifo_out[33];
+   assign      Tx_mac_eop = (prot_state == PROT_TRAIL); // sfifo_out[32];
+
+   // BUFFER side signals
+   reg                xfer_active;
+   always @(posedge clk)
+     if(rst)
+       xfer_active <= 0;
+     else if(rd_eop_i & ~full)
+       xfer_active <= 0;
+     else if(rd_sop_i)
+       xfer_active <= 1;
+   
+   assign      sfifo_in = {rd_sop_i, rd_eop_i, rd_dat_i};
+   assign      sfifo_write = xfer_active & ~full;
+
+   assign      rd_read_o = sfifo_write;
+   assign      rd_done_o = 0;  // Always send everything we're given?
+   assign      rd_error_o = 0;  // No possible error situations?
+   
+endmodule // tx_prot_engine