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[Commit-gnuradio] r7378 - in usrp2/trunk/fpga/opencores/aemb/rtl/verilog
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r7378 - in usrp2/trunk/fpga/opencores/aemb/rtl/verilog: . CVS |
|
Date: |
Tue, 8 Jan 2008 12:41:45 -0700 (MST) |
Author: matt
Date: 2008-01-08 12:41:44 -0700 (Tue, 08 Jan 2008)
New Revision: 7378
Added:
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v
Modified:
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v
Log:
catch up to shawn's latest. Barrel shifter has pipelining, but control doesn't
work yet
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries 2008-01-08
02:18:37 UTC (rev 7377)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/CVS/Entries 2008-01-08
19:41:44 UTC (rev 7378)
@@ -1,15 +1,18 @@
-/aeMB_bpcu.v/1.4/Sat Nov 24 05:11:03 2007//
-/aeMB_core.v/1.9/Mon Nov 26 06:53:03 2007//
-/aeMB_ibuf.v/1.7/Mon Nov 26 06:53:03 2007//
-/aeMB_regf.v/1.3/Sat Nov 24 05:11:03 2007//
-/aeMB2_aslu.v/1.1/Tue Dec 11 00:43:17 2007//
-/aeMB2_bpcu.v/1.1/Tue Dec 11 00:43:17 2007//
-/aeMB2_edk32.v/1.2/Tue Dec 11 00:43:17 2007//
-/aeMB2_idmx.v/1.1/Tue Dec 11 00:43:17 2007//
-/aeMB2_opmx.v/1.1/Tue Dec 11 00:43:17 2007//
-/aeMB2_regf.v/1.1/Tue Dec 11 00:43:17 2007//
-/aeMB2_sysc.v/1.1/Tue Dec 11 00:43:17 2007//
-/aeMB_ctrl.v/1.10/Wed Dec 12 03:12:13 2007//
-/aeMB_edk32.v/1.11/Wed Dec 12 03:12:13 2007//
-/aeMB_xecu.v/1.9/Wed Dec 12 03:12:13 2007//
+/aeMB_bpcu.v/1.4/Tue Jan 8 19:38:58 2008//
+/aeMB_core.v/1.9/Tue Jan 8 19:38:58 2008//
+/aeMB_ctrl.v/1.10/Tue Jan 8 19:38:58 2008//
+/aeMB_edk32.v/1.13/Tue Jan 8 19:38:58 2008//
+/aeMB_ibuf.v/1.8/Tue Jan 8 19:38:58 2008//
+/aeMB_regf.v/1.3/Tue Jan 8 19:38:58 2008//
+/aeMB_sim.v/1.1/Tue Jan 8 19:38:59 2008//
+/aeMB_xecu.v/1.10/Tue Jan 8 19:38:59 2008//
+/aeMB2_aslu.v/1.7/Tue Jan 8 19:39:38 2008//
+/aeMB2_bpcu.v/1.5/Tue Jan 8 19:39:38 2008//
+/aeMB2_edk32.v/1.8/Tue Jan 8 19:39:38 2008//
+/aeMB2_idmx.v/1.5/Tue Jan 8 19:39:38 2008//
+/aeMB2_ofid.v/1.2/Tue Jan 8 19:39:38 2008//
+/aeMB2_opmx.v/1.3/Tue Jan 8 19:39:38 2008//
+/aeMB2_regf.v/1.3/Tue Jan 8 19:39:38 2008//
+/aeMB2_sim.v/1.2/Tue Jan 8 19:39:38 2008//
+/aeMB2_sysc.v/1.5/Tue Jan 8 19:39:39 2008//
D
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v 2008-01-08
02:18:37 UTC (rev 7377)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v 2008-01-08
19:41:44 UTC (rev 7378)
@@ -1,62 +1,23 @@
-// $Id: aeMB_edk32.v,v 1.11 2007/11/30 17:08:29 sybreon Exp $
-//
-// AEMB EDK 3.2 Compatible Core
-//
-// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
-//
-// This file is part of AEMB.
-//
-// AEMB is free software: you can redistribute it and/or modify it
-// under the terms of the GNU Lesser General Public License as
-// published by the Free Software Foundation, either version 3 of the
-// License, or (at your option) any later version.
-//
-// AEMB is distributed in the hope that it will be useful, but WITHOUT
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-// Public License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public
-// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
-//
-// $Log: aeMB_edk32.v,v $
-// Revision 1.11 2007/11/30 17:08:29 sybreon
-// Moved simulation kernel into code.
-//
-// Revision 1.10 2007/11/16 21:52:03 sybreon
-// Added fsl_tag_o to FSL bus (tag either address or data).
-//
-// Revision 1.9 2007/11/14 23:19:24 sybreon
-// Fixed minor typo.
-//
-// Revision 1.8 2007/11/14 22:14:34 sybreon
-// Changed interrupt handling system (reported by M. Ettus).
-//
-// Revision 1.7 2007/11/10 16:39:38 sybreon
-// Upgraded license to LGPLv3.
-// Significant performance optimisations.
-//
-// Revision 1.6 2007/11/09 20:51:52 sybreon
-// Added GET/PUT support through a FSL bus.
-//
-// Revision 1.5 2007/11/08 17:48:14 sybreon
-// Fixed data WISHBONE arbitration problem (reported by J Lee).
-//
-// Revision 1.4 2007/11/08 14:17:47 sybreon
-// Parameterised optional components.
-//
-// Revision 1.3 2007/11/03 08:34:55 sybreon
-// Minor code cleanup.
-//
-// Revision 1.2 2007/11/02 19:20:58 sybreon
-// Added better (beta) interrupt support.
-// Changed MSR_IE to disabled at reset as per MB docs.
-//
-// Revision 1.1 2007/11/02 03:25:40 sybreon
-// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
-// Fixed various minor data hazard bugs.
-// Code compatible with -O0/1/2/3/s generated code.
-//
+/* $Id: aeMB_edk32.v,v 1.13 2007/12/25 22:15:09 sybreon Exp $
+**
+** AEMB EDK 3.2 Compatible Core
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
module aeMB_edk32 (/*AUTOARG*/
// Outputs
@@ -125,15 +86,16 @@
wire [31:0] rRESULT; // From xecu of aeMB_xecu.v
wire [4:0] rRW; // From ctrl of aeMB_ctrl.v
wire [31:0] rSIMM; // From ibuf of aeMB_ibuf.v
+ wire rSTALL; // From ibuf of
aeMB_ibuf.v
wire [31:0] xIREG; // From ibuf of aeMB_ibuf.v
// End of automatics
input sys_clk_i;
input sys_rst_i;
-
+
wire grst = sys_rst_i;
wire gclk = sys_clk_i;
- wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^
fsl_ack_i) | !iwb_ack_i);
+ wire gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^
fsl_ack_i) | !iwb_ack_i) & !rSTALL;
// --- INSTANTIATIONS -------------------------------------
@@ -148,6 +110,7 @@
.rOPC (rOPC[5:0]),
.rSIMM (rSIMM[31:0]),
.xIREG (xIREG[31:0]),
+ .rSTALL (rSTALL),
.iwb_stb_o (iwb_stb_o),
// Inputs
.rBRA (rBRA),
@@ -260,6 +223,7 @@
.rBRA (rBRA),
.rDLY (rDLY),
.rALT (rALT[10:0]),
+ .rSTALL (rSTALL),
.rSIMM (rSIMM[31:0]),
.rIMM (rIMM[15:0]),
.rOPC (rOPC[5:0]),
@@ -269,205 +233,52 @@
.gclk (gclk),
.grst (grst),
.gena (gena));
-
- // --- SIMULATION KERNEL ----------------------------------
- // synopsys translate_off
-
-`ifdef AEMB_SIMULATION_KERNEL
-
- wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0};
- wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0};
- wire [1:0] wBRA = {rBRA, rDLY};
- wire [3:0] wMSR = {xecu.rMSR_BIP, xecu.rMSR_C, xecu.rMSR_IE,
xecu.rMSR_BE};
-
- always @(posedge gclk) if (gena) begin
- $write ("\n", ($stime/10));
- $writeh (" PC=", iwb_adr );
- $writeh ("\t");
-
- case (wBRA)
- 2'b00: $write(" ");
- 2'b01: $write(".");
- 2'b10: $write("-");
- 2'b11: $write("+");
- endcase // case (wBRA)
-
- case (rOPC)
- 6'o00: if (rRD == 0) $write(" "); else $write("ADD");
- 6'o01: $write("RSUB");
- 6'o02: $write("ADDC");
- 6'o03: $write("RSUBC");
- 6'o04: $write("ADDK");
- 6'o05: case (rIMM[1:0])
- 2'o0: $write("RSUBK");
- 2'o1: $write("CMP");
- 2'o3: $write("CMPU");
- default: $write("XXX");
- endcase // case (rIMM[1:0])
- 6'o06: $write("ADDKC");
- 6'o07: $write("RSUBKC");
-
- 6'o10: $write("ADDI");
- 6'o11: $write("RSUBI");
- 6'o12: $write("ADDIC");
- 6'o13: $write("RSUBIC");
- 6'o14: $write("ADDIK");
- 6'o15: $write("RSUBIK");
- 6'o16: $write("ADDIKC");
- 6'o17: $write("RSUBIKC");
+endmodule // aeMB_edk32
- 6'o20: $write("MUL");
- 6'o21: case (rALT[10:9])
- 2'o0: $write("BSRL");
- 2'o1: $write("BSRA");
- 2'o2: $write("BSLL");
- default: $write("XXX");
- endcase // case (rALT[10:9])
- 6'o22: $write("IDIV");
+/*
+ $Log: aeMB_edk32.v,v $
+ Revision 1.13 2007/12/25 22:15:09 sybreon
+ Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
- 6'o30: $write("MULI");
- 6'o31: case (rALT[10:9])
- 2'o0: $write("BSRLI");
- 2'o1: $write("BSRAI");
- 2'o2: $write("BSLLI");
- default: $write("XXX");
- endcase // case (rALT[10:9])
- 6'o33: case (rRB[4:2])
- 3'o0: $write("GET");
- 3'o4: $write("PUT");
- 3'o2: $write("NGET");
- 3'o6: $write("NPUT");
- 3'o1: $write("CGET");
- 3'o5: $write("CPUT");
- 3'o3: $write("NCGET");
- 3'o7: $write("NCPUT");
- endcase // case (rRB[4:2])
+ Revision 1.12 2007/12/23 20:40:44 sybreon
+ Abstracted simulation kernel (aeMB_sim) to split simulation models from
synthesis models.
- 6'o40: $write("OR");
- 6'o41: $write("AND");
- 6'o42: if (rRD == 0) $write(" "); else $write("XOR");
- 6'o43: $write("ANDN");
- 6'o44: case (rIMM[6:5])
- 2'o0: $write("SRA");
- 2'o1: $write("SRC");
- 2'o2: $write("SRL");
- 2'o3: if (rIMM[0]) $write("SEXT16"); else $write("SEXT8");
- endcase // case (rIMM[6:5])
-
- 6'o45: $write("MOV");
- 6'o46: case (rRA[3:2])
- 3'o0: $write("BR");
- 3'o1: $write("BRL");
- 3'o2: $write("BRA");
- 3'o3: $write("BRAL");
- endcase // case (rRA[3:2])
-
- 6'o47: case (rRD[2:0])
- 3'o0: $write("BEQ");
- 3'o1: $write("BNE");
- 3'o2: $write("BLT");
- 3'o3: $write("BLE");
- 3'o4: $write("BGT");
- 3'o5: $write("BGE");
- default: $write("XXX");
- endcase // case (rRD[2:0])
-
- 6'o50: $write("ORI");
- 6'o51: $write("ANDI");
- 6'o52: $write("XORI");
- 6'o53: $write("ANDNI");
- 6'o54: $write("IMMI");
- 6'o55: case (rRD[1:0])
- 2'o0: $write("RTSD");
- 2'o1: $write("RTID");
- 2'o2: $write("RTBD");
- default: $write("XXX");
- endcase // case (rRD[1:0])
- 6'o56: case (rRA[3:2])
- 3'o0: $write("BRI");
- 3'o1: $write("BRLI");
- 3'o2: $write("BRAI");
- 3'o3: $write("BRALI");
- endcase // case (rRA[3:2])
- 6'o57: case (rRD[2:0])
- 3'o0: $write("BEQI");
- 3'o1: $write("BNEI");
- 3'o2: $write("BLTI");
- 3'o3: $write("BLEI");
- 3'o4: $write("BGTI");
- 3'o5: $write("BGEI");
- default: $write("XXX");
- endcase // case (rRD[2:0])
-
- 6'o60: $write("LBU");
- 6'o61: $write("LHU");
- 6'o62: $write("LW");
- 6'o64: $write("SB");
- 6'o65: $write("SH");
- 6'o66: $write("SW");
-
- 6'o70: $write("LBUI");
- 6'o71: $write("LHUI");
- 6'o72: $write("LWI");
- 6'o74: $write("SBI");
- 6'o75: $write("SHI");
- 6'o76: $write("SWI");
+ Revision 1.11 2007/11/30 17:08:29 sybreon
+ Moved simulation kernel into code.
+
+ Revision 1.10 2007/11/16 21:52:03 sybreon
+ Added fsl_tag_o to FSL bus (tag either address or data).
- default: $write("XXX");
- endcase // case (rOPC)
+ Revision 1.9 2007/11/14 23:19:24 sybreon
+ Fixed minor typo.
- case (rOPC[3])
- 1'b1: $writeh("\tr",rRD,", r",rRA,", h",rIMM);
- 1'b0: $writeh("\tr",rRD,", r",rRA,", r",rRB," ");
- endcase // case (rOPC[3])
+ Revision 1.8 2007/11/14 22:14:34 sybreon
+ Changed interrupt handling system (reported by M. Ettus).
-
- // ALU
- $write("\t");
- $writeh(" A=",xecu.rOPA);
- $writeh(" B=",xecu.rOPB);
-
- case (rMXALU)
- 3'o0: $write(" ADD");
- 3'o1: $write(" LOG");
- 3'o2: $write(" SFT");
- 3'o3: $write(" MOV");
- 3'o4: $write(" MUL");
- 3'o5: $write(" BSF");
- default: $write(" XXX");
- endcase // case (rMXALU)
- $writeh("=h",xecu.xRESULT);
+ Revision 1.7 2007/11/10 16:39:38 sybreon
+ Upgraded license to LGPLv3.
+ Significant performance optimisations.
- // WRITEBACK
- $writeh("\tSR=", wMSR," ");
-
- if (regf.fRDWE) begin
- case (rMXDST)
- 2'o2: begin
- if (dwb_stb_o) $writeh("R",rRW,"=RAM(h",regf.xWDAT,")");
- if (fsl_stb_o) $writeh("R",rRW,"=FSL(h",regf.xWDAT,")");
- end
- 2'o1: $writeh("R",rRW,"=LNK(h",regf.xWDAT,")");
- 2'o0: $writeh("R",rRW,"=ALU(h",regf.xWDAT,")");
- endcase // case (rMXDST)
- end
-
- // STORE
- if (dwb_stb_o & dwb_wre_o) begin
- $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
- case (dwb_sel_o)
- 4'hF: $write(":L");
- 4'h3,4'hC: $write(":W");
- 4'h1,4'h2,4'h4,4'h8: $write(":B");
- endcase // case (dwb_sel_o)
-
- end
-
- end // if (gena)
-
-`endif // `ifdef AEMB_SIMULATION_KERNEL
- // synopsys translate_on
-
-endmodule // aeMB_edk32
+ Revision 1.6 2007/11/09 20:51:52 sybreon
+ Added GET/PUT support through a FSL bus.
+
+ Revision 1.5 2007/11/08 17:48:14 sybreon
+ Fixed data WISHBONE arbitration problem (reported by J Lee).
+
+ Revision 1.4 2007/11/08 14:17:47 sybreon
+ Parameterised optional components.
+
+ Revision 1.3 2007/11/03 08:34:55 sybreon
+ Minor code cleanup.
+
+ Revision 1.2 2007/11/02 19:20:58 sybreon
+ Added better (beta) interrupt support.
+ Changed MSR_IE to disabled at reset as per MB docs.
+
+ Revision 1.1 2007/11/02 03:25:40 sybreon
+ New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+ Fixed various minor data hazard bugs.
+ Code compatible with -O0/1/2/3/s generated code.
+*/
\ No newline at end of file
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v 2008-01-08
02:18:37 UTC (rev 7377)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v 2008-01-08
19:41:44 UTC (rev 7378)
@@ -1,54 +1,27 @@
-// $Id: aeMB_ibuf.v,v 1.7 2007/11/22 15:11:15 sybreon Exp $
-//
-// AEMB INSTRUCTION BUFFER
-//
-// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
-//
-// This file is part of AEMB.
-//
-// AEMB is free software: you can redistribute it and/or modify it
-// under the terms of the GNU Lesser General Public License as
-// published by the Free Software Foundation, either version 3 of the
-// License, or (at your option) any later version.
-//
-// AEMB is distributed in the hope that it will be useful, but WITHOUT
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-// Public License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public
-// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
-//
-// $Log: aeMB_ibuf.v,v $
-// Revision 1.7 2007/11/22 15:11:15 sybreon
-// Change interrupt to positive level triggered interrupts.
-//
-// Revision 1.6 2007/11/14 23:39:51 sybreon
-// Fixed interrupt signal synchronisation.
-//
-// Revision 1.5 2007/11/14 22:14:34 sybreon
-// Changed interrupt handling system (reported by M. Ettus).
-//
-// Revision 1.4 2007/11/10 16:39:38 sybreon
-// Upgraded license to LGPLv3.
-// Significant performance optimisations.
-//
-// Revision 1.3 2007/11/03 08:34:55 sybreon
-// Minor code cleanup.
-//
-// Revision 1.2 2007/11/02 19:20:58 sybreon
-// Added better (beta) interrupt support.
-// Changed MSR_IE to disabled at reset as per MB docs.
-//
-// Revision 1.1 2007/11/02 03:25:40 sybreon
-// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
-// Fixed various minor data hazard bugs.
-// Code compatible with -O0/1/2/3/s generated code.
-//
+/* $Id: aeMB_ibuf.v,v 1.8 2007/12/25 22:15:09 sybreon Exp $
+**
+** AEMB INSTRUCTION BUFFER
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
module aeMB_ibuf (/*AUTOARG*/
// Outputs
- rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, iwb_stb_o,
+ rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
// Inputs
rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
grst, gena
@@ -60,6 +33,7 @@
output [5:0] rOPC;
output [31:0] rSIMM;
output [31:0] xIREG;
+ output rSTALL;
input rBRA;
//input [1:0] rXCE;
@@ -89,6 +63,7 @@
assign iwb_stb_o = 1'b1;
reg [31:0] rSIMM, xSIMM;
+ reg rSTALL;
wire [31:0] wXCEOP = 32'hBA2D0008; // Vector 0x08
wire [31:0] wINTOP = 32'hB9CE0010; // Vector 0x10
@@ -154,6 +129,53 @@
{rOPC, rRD, rRA, rIMM} <= #1 xIREG;
rSIMM <= #1 xSIMM;
end
+
+ // --- STALL FOR MUL/BSF -----------------------------------
+
+ wire [5:0] wOPC = xIREG[31:26];
+ wire fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
+ wire fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rSTALL <= 1'h0;
+ // End of automatics
+ end else begin
+ rSTALL <= #1 !rSTALL & (fMUL | fBSF);
+ end
+
endmodule // aeMB_ibuf
+
+/*
+ $Log: aeMB_ibuf.v,v $
+ Revision 1.8 2007/12/25 22:15:09 sybreon
+ Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
+
+ Revision 1.7 2007/11/22 15:11:15 sybreon
+ Change interrupt to positive level triggered interrupts.
+
+ Revision 1.6 2007/11/14 23:39:51 sybreon
+ Fixed interrupt signal synchronisation.
+
+ Revision 1.5 2007/11/14 22:14:34 sybreon
+ Changed interrupt handling system (reported by M. Ettus).
+
+ Revision 1.4 2007/11/10 16:39:38 sybreon
+ Upgraded license to LGPLv3.
+ Significant performance optimisations.
+
+ Revision 1.3 2007/11/03 08:34:55 sybreon
+ Minor code cleanup.
+
+ Revision 1.2 2007/11/02 19:20:58 sybreon
+ Added better (beta) interrupt support.
+ Changed MSR_IE to disabled at reset as per MB docs.
+
+ Revision 1.1 2007/11/02 03:25:40 sybreon
+ New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+ Fixed various minor data hazard bugs.
+ Code compatible with -O0/1/2/3/s generated code.
+*/
\ No newline at end of file
Added: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v
(rev 0)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v 2008-01-08
19:41:44 UTC (rev 7378)
@@ -0,0 +1,306 @@
+/* $Id: aeMB_sim.v,v 1.1 2007/12/23 20:40:45 sybreon Exp $
+**
+** AEMB EDK 3.2 Compatible Core
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+module aeMB_sim (/*AUTOARG*/
+ // Outputs
+ iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
+ fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
+ // Inputs
+ sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
+ fsl_ack_i, dwb_dat_i, dwb_ack_i
+ );
+ // Bus widths
+ parameter IW = 32; /// Instruction bus address width
+ parameter DW = 32; /// Data bus address width
+
+ // Optional functions
+ parameter MUL = 1; // Multiplier
+ parameter BSF = 1; // Barrel Shifter
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [DW-1:2] dwb_adr_o; // From cpu of aeMB_edk32.v
+ output [31:0] dwb_dat_o; // From cpu of aeMB_edk32.v
+ output [3:0] dwb_sel_o; // From cpu of
aeMB_edk32.v
+ output dwb_stb_o; // From cpu of aeMB_edk32.v
+ output dwb_wre_o; // From cpu of aeMB_edk32.v
+ output [6:2] fsl_adr_o; // From cpu of
aeMB_edk32.v
+ output [31:0] fsl_dat_o; // From cpu of aeMB_edk32.v
+ output fsl_stb_o; // From cpu of aeMB_edk32.v
+ output [1:0] fsl_tag_o; // From cpu of
aeMB_edk32.v
+ output fsl_wre_o; // From cpu of aeMB_edk32.v
+ output [IW-1:2] iwb_adr_o; // From cpu of aeMB_edk32.v
+ output iwb_stb_o; // From cpu of aeMB_edk32.v
+ // End of automatics
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input dwb_ack_i; // To cpu of aeMB_edk32.v
+ input [31:0] dwb_dat_i; // To cpu of
aeMB_edk32.v
+ input fsl_ack_i; // To cpu of aeMB_edk32.v
+ input [31:0] fsl_dat_i; // To cpu of
aeMB_edk32.v
+ input iwb_ack_i; // To cpu of aeMB_edk32.v
+ input [31:0] iwb_dat_i; // To cpu of
aeMB_edk32.v
+ input sys_clk_i; // To cpu of aeMB_edk32.v
+ input sys_int_i; // To cpu of aeMB_edk32.v
+ input sys_rst_i; // To cpu of aeMB_edk32.v
+ // End of automatics
+ /*AUTOWIRE*/
+
+ aeMB_edk32
+ #(/*AUTOINSTPARAM*/
+ // Parameters
+ .IW (IW),
+ .DW (DW),
+ .MUL (MUL),
+ .BSF (BSF))
+ cpu
+ (/*AUTOINST*/
+ // Outputs
+ .dwb_adr_o (dwb_adr_o[DW-1:2]),
+ .dwb_dat_o (dwb_dat_o[31:0]),
+ .dwb_sel_o (dwb_sel_o[3:0]),
+ .dwb_stb_o (dwb_stb_o),
+ .dwb_wre_o (dwb_wre_o),
+ .fsl_adr_o (fsl_adr_o[6:2]),
+ .fsl_dat_o (fsl_dat_o[31:0]),
+ .fsl_stb_o (fsl_stb_o),
+ .fsl_tag_o (fsl_tag_o[1:0]),
+ .fsl_wre_o (fsl_wre_o),
+ .iwb_adr_o (iwb_adr_o[IW-1:2]),
+ .iwb_stb_o (iwb_stb_o),
+ // Inputs
+ .dwb_ack_i (dwb_ack_i),
+ .dwb_dat_i (dwb_dat_i[31:0]),
+ .fsl_ack_i (fsl_ack_i),
+ .fsl_dat_i (fsl_dat_i[31:0]),
+ .iwb_ack_i (iwb_ack_i),
+ .iwb_dat_i (iwb_dat_i[31:0]),
+ .sys_int_i (sys_int_i),
+ .sys_clk_i (sys_clk_i),
+ .sys_rst_i (sys_rst_i));
+
+ // --- SIMULATION KERNEL ----------------------------------
+ // synopsys translate_off
+
+ wire [IW-1:0] iwb_adr = {iwb_adr_o, 2'd0};
+ wire [DW-1:0] dwb_adr = {dwb_adr_o,2'd0};
+ wire [1:0] wBRA = {cpu.rBRA, cpu.rDLY};
+ wire [3:0] wMSR = {cpu.xecu.rMSR_BIP, cpu.xecu.rMSR_C,
cpu.xecu.rMSR_IE, cpu.xecu.rMSR_BE};
+
+ always @(posedge cpu.gclk) begin
+ if (cpu.gena) begin
+
+ $write ("\n", ($stime/10));
+ $writeh (" PC=", iwb_adr );
+ $writeh ("\t");
+
+ case (wBRA)
+ 2'b00: $write(" ");
+ 2'b01: $write(".");
+ 2'b10: $write("-");
+ 2'b11: $write("+");
+ endcase // case (cpu.wBRA)
+
+ case (cpu.rOPC)
+ 6'o00: if (cpu.rRD == 0) $write(" "); else $write("ADD");
+ 6'o01: $write("RSUB");
+ 6'o02: $write("ADDC");
+ 6'o03: $write("RSUBC");
+ 6'o04: $write("ADDK");
+ 6'o05: case (cpu.rIMM[1:0])
+ 2'o0: $write("RSUBK");
+ 2'o1: $write("CMP");
+ 2'o3: $write("CMPU");
+ default: $write("XXX");
+ endcase // case (cpu.rIMM[1:0])
+ 6'o06: $write("ADDKC");
+ 6'o07: $write("RSUBKC");
+
+ 6'o10: $write("ADDI");
+ 6'o11: $write("RSUBI");
+ 6'o12: $write("ADDIC");
+ 6'o13: $write("RSUBIC");
+ 6'o14: $write("ADDIK");
+ 6'o15: $write("RSUBIK");
+ 6'o16: $write("ADDIKC");
+ 6'o17: $write("RSUBIKC");
+
+ 6'o20: $write("MUL");
+ 6'o21: case (cpu.rALT[10:9])
+ 2'o0: $write("BSRL");
+ 2'o1: $write("BSRA");
+ 2'o2: $write("BSLL");
+ default: $write("XXX");
+ endcase // case (cpu.rALT[10:9])
+ 6'o22: $write("IDIV");
+
+ 6'o30: $write("MULI");
+ 6'o31: case (cpu.rALT[10:9])
+ 2'o0: $write("BSRLI");
+ 2'o1: $write("BSRAI");
+ 2'o2: $write("BSLLI");
+ default: $write("XXX");
+ endcase // case (cpu.rALT[10:9])
+ 6'o33: case (cpu.rRB[4:2])
+ 3'o0: $write("GET");
+ 3'o4: $write("PUT");
+ 3'o2: $write("NGET");
+ 3'o6: $write("NPUT");
+ 3'o1: $write("CGET");
+ 3'o5: $write("CPUT");
+ 3'o3: $write("NCGET");
+ 3'o7: $write("NCPUT");
+ endcase // case (cpu.rRB[4:2])
+
+ 6'o40: $write("OR");
+ 6'o41: $write("AND");
+ 6'o42: if (cpu.rRD == 0) $write(" "); else $write("XOR");
+ 6'o43: $write("ANDN");
+ 6'o44: case (cpu.rIMM[6:5])
+ 2'o0: $write("SRA");
+ 2'o1: $write("SRC");
+ 2'o2: $write("SRL");
+ 2'o3: if (cpu.rIMM[0]) $write("SEXT16"); else
$write("SEXT8");
+ endcase // case (cpu.rIMM[6:5])
+
+ 6'o45: $write("MOV");
+ 6'o46: case (cpu.rRA[3:2])
+ 3'o0: $write("BR");
+ 3'o1: $write("BRL");
+ 3'o2: $write("BRA");
+ 3'o3: $write("BRAL");
+ endcase // case (cpu.rRA[3:2])
+
+ 6'o47: case (cpu.rRD[2:0])
+ 3'o0: $write("BEQ");
+ 3'o1: $write("BNE");
+ 3'o2: $write("BLT");
+ 3'o3: $write("BLE");
+ 3'o4: $write("BGT");
+ 3'o5: $write("BGE");
+ default: $write("XXX");
+ endcase // case (cpu.rRD[2:0])
+
+ 6'o50: $write("ORI");
+ 6'o51: $write("ANDI");
+ 6'o52: $write("XORI");
+ 6'o53: $write("ANDNI");
+ 6'o54: $write("IMMI");
+ 6'o55: case (cpu.rRD[1:0])
+ 2'o0: $write("RTSD");
+ 2'o1: $write("RTID");
+ 2'o2: $write("RTBD");
+ default: $write("XXX");
+ endcase // case (cpu.rRD[1:0])
+ 6'o56: case (cpu.rRA[3:2])
+ 3'o0: $write("BRI");
+ 3'o1: $write("BRLI");
+ 3'o2: $write("BRAI");
+ 3'o3: $write("BRALI");
+ endcase // case (cpu.rRA[3:2])
+ 6'o57: case (cpu.rRD[2:0])
+ 3'o0: $write("BEQI");
+ 3'o1: $write("BNEI");
+ 3'o2: $write("BLTI");
+ 3'o3: $write("BLEI");
+ 3'o4: $write("BGTI");
+ 3'o5: $write("BGEI");
+ default: $write("XXX");
+ endcase // case (cpu.rRD[2:0])
+
+ 6'o60: $write("LBU");
+ 6'o61: $write("LHU");
+ 6'o62: $write("LW");
+ 6'o64: $write("SB");
+ 6'o65: $write("SH");
+ 6'o66: $write("SW");
+
+ 6'o70: $write("LBUI");
+ 6'o71: $write("LHUI");
+ 6'o72: $write("LWI");
+ 6'o74: $write("SBI");
+ 6'o75: $write("SHI");
+ 6'o76: $write("SWI");
+
+ default: $write("XXX");
+ endcase // case (cpu.rOPC)
+
+ case (cpu.rOPC[3])
+ 1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM);
+ 1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB," ");
+ endcase // case (cpu.rOPC[3])
+
+
+ // ALU
+ $write("\t");
+ $writeh(" A=",cpu.xecu.rOPA);
+ $writeh(" B=",cpu.xecu.rOPB);
+
+ case (cpu.rMXALU)
+ 3'o0: $write(" ADD");
+ 3'o1: $write(" LOG");
+ 3'o2: $write(" SFT");
+ 3'o3: $write(" MOV");
+ 3'o4: $write(" MUL");
+ 3'o5: $write(" BSF");
+ default: $write(" XXX");
+ endcase // case (cpu.rMXALU)
+ $writeh("=h",cpu.xecu.xRESULT);
+
+ // WRITEBACK
+ $writeh("\tSR=", wMSR," ");
+
+ if (cpu.regf.fRDWE) begin
+ case (cpu.rMXDST)
+ 2'o2: begin
+ if (dwb_stb_o)
$writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")");
+ if (fsl_stb_o)
$writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")");
+ end
+ 2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")");
+ 2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")");
+ endcase // case (cpu.rMXDST)
+ end
+
+ // STORE
+ if (dwb_stb_o & dwb_wre_o) begin
+ $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
+ case (dwb_sel_o)
+ 4'hF: $write(":L");
+ 4'h3,4'hC: $write(":W");
+ 4'h1,4'h2,4'h4,4'h8: $write(":B");
+ endcase // case (dwb_sel_o)
+
+ end
+
+ end // if (cpu.gena)
+
+ end // always @ (posedge cpu.gclk)
+
+ // synopsys translate_on
+
+endmodule // aeMB_sim
+
+/*
+ $Log: aeMB_sim.v,v $
+ Revision 1.1 2007/12/23 20:40:45 sybreon
+ Abstracted simulation kernel (aeMB_sim) to split simulation models from
synthesis models.
+
+ */
\ No newline at end of file
Modified: usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v
===================================================================
--- usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v 2008-01-08
02:18:37 UTC (rev 7377)
+++ usrp2/trunk/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v 2008-01-08
19:41:44 UTC (rev 7378)
@@ -1,56 +1,23 @@
-// $Id: aeMB_xecu.v,v 1.9 2007/11/30 16:42:51 sybreon Exp $
-//
-// AEMB MAIN EXECUTION ALU
-//
-// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
-//
-// This file is part of AEMB.
-//
-// AEMB is free software: you can redistribute it and/or modify it
-// under the terms of the GNU Lesser General Public License as
-// published by the Free Software Foundation, either version 3 of the
-// License, or (at your option) any later version.
-//
-// AEMB is distributed in the hope that it will be useful, but WITHOUT
-// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-// or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
-// Public License for more details.
-//
-// You should have received a copy of the GNU Lesser General Public
-// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
-//
-// $Log: aeMB_xecu.v,v $
-// Revision 1.9 2007/11/30 16:42:51 sybreon
-// Minor code cleanup.
-//
-// Revision 1.8 2007/11/16 21:52:03 sybreon
-// Added fsl_tag_o to FSL bus (tag either address or data).
-//
-// Revision 1.7 2007/11/14 22:14:34 sybreon
-// Changed interrupt handling system (reported by M. Ettus).
-//
-// Revision 1.6 2007/11/10 16:39:38 sybreon
-// Upgraded license to LGPLv3.
-// Significant performance optimisations.
-//
-// Revision 1.5 2007/11/09 20:51:52 sybreon
-// Added GET/PUT support through a FSL bus.
-//
-// Revision 1.4 2007/11/08 14:17:47 sybreon
-// Parameterised optional components.
-//
-// Revision 1.3 2007/11/03 08:34:55 sybreon
-// Minor code cleanup.
-//
-// Revision 1.2 2007/11/02 19:20:58 sybreon
-// Added better (beta) interrupt support.
-// Changed MSR_IE to disabled at reset as per MB docs.
-//
-// Revision 1.1 2007/11/02 03:25:41 sybreon
-// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
-// Fixed various minor data hazard bugs.
-// Code compatible with -O0/1/2/3/s generated code.
-//
+/* $Id: aeMB_xecu.v,v 1.10 2007/12/25 22:15:09 sybreon Exp $
+**
+** AEMB MAIN EXECUTION ALU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
module aeMB_xecu (/*AUTOARG*/
// Outputs
@@ -58,7 +25,7 @@
rMSR_IE, rMSR_BIP,
// Inputs
rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT,
- rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
+ rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
);
parameter DW=32;
@@ -84,7 +51,8 @@
input [2:0] rMXALU;
input rBRA, rDLY;
input [10:0] rALT;
-
+
+ input rSTALL;
input [31:0] rSIMM;
input [15:0] rIMM;
input [5:0] rOPC;
@@ -193,11 +161,22 @@
// --- MULTIPLIER ------------------------------------------
// TODO: 2 stage multiplier
- reg [31:0] rRES_MUL;
+ reg [31:0] rRES_MUL, rRES_MUL0, xRES_MUL;
always @(/*AUTOSENSE*/rOPA or rOPB) begin
- rRES_MUL <= (rOPA * rOPB);
+ xRES_MUL <= (rOPA * rOPB);
end
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rRES_MUL <= 32'h0;
+ // End of automatics
+ end else if (rSTALL) begin
+ rRES_MUL <= #1 xRES_MUL;
+ end
+
+
// --- BARREL SHIFTER --------------------------------------
reg [31:0] rRES_BSF;
@@ -248,11 +227,27 @@
5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
endcase // case (rOPB[4:0])
- always @(/*AUTOSENSE*/rALT or xBSLL or xBSRA or xBSRL)
+ reg [31:0] rBSRL, rBSRA, rBSLL;
+
+ always @(posedge gclk)
+ if (grst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rBSLL <= 32'h0;
+ rBSRA <= 32'h0;
+ rBSRL <= 32'h0;
+ // End of automatics
+ end else if (rSTALL) begin
+ rBSRL <= #1 xBSRL;
+ rBSRA <= #1 xBSRA;
+ rBSLL <= #1 xBSLL;
+ end
+
+ always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL)
case (rALT[10:9])
- 2'd0: rRES_BSF <= xBSRL;
- 2'd1: rRES_BSF <= xBSRA;
- 2'd2: rRES_BSF <= xBSLL;
+ 2'd0: rRES_BSF <= rBSRL;
+ 2'd1: rRES_BSF <= rBSRA;
+ 2'd2: rRES_BSF <= rBSLL;
default: rRES_BSF <= 32'hX;
endcase // case (rALT[10:9])
@@ -373,7 +368,45 @@
rMSR_IE <= #1 xMSR_IE;
rMSR_BE <= #1 xMSR_BE;
rMSR_BIP <= #1 xMSR_BIP;
- rFSLADR <= #1 xFSLADR;
+ rFSLADR <= #1 xFSLADR;
end
endmodule // aeMB_xecu
+
+/*
+ $Log: aeMB_xecu.v,v $
+ Revision 1.10 2007/12/25 22:15:09 sybreon
+ Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
+
+ Revision 1.9 2007/11/30 16:42:51 sybreon
+ Minor code cleanup.
+
+ Revision 1.8 2007/11/16 21:52:03 sybreon
+ Added fsl_tag_o to FSL bus (tag either address or data).
+
+ Revision 1.7 2007/11/14 22:14:34 sybreon
+ Changed interrupt handling system (reported by M. Ettus).
+
+ Revision 1.6 2007/11/10 16:39:38 sybreon
+ Upgraded license to LGPLv3.
+ Significant performance optimisations.
+
+ Revision 1.5 2007/11/09 20:51:52 sybreon
+ Added GET/PUT support through a FSL bus.
+
+ Revision 1.4 2007/11/08 14:17:47 sybreon
+ Parameterised optional components.
+
+ Revision 1.3 2007/11/03 08:34:55 sybreon
+ Minor code cleanup.
+
+ Revision 1.2 2007/11/02 19:20:58 sybreon
+ Added better (beta) interrupt support.
+ Changed MSR_IE to disabled at reset as per MB docs.
+
+ Revision 1.1 2007/11/02 03:25:41 sybreon
+ New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+ Fixed various minor data hazard bugs.
+ Code compatible with -O0/1/2/3/s generated code.
+
+*/
\ No newline at end of file
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- [Commit-gnuradio] r7378 - in usrp2/trunk/fpga/opencores/aemb/rtl/verilog: . CVS,
matt <=