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[Commit-gnuradio] r7401 - usrp2/trunk/fpga/eth


From: matt
Subject: [Commit-gnuradio] r7401 - usrp2/trunk/fpga/eth
Date: Fri, 11 Jan 2008 01:46:22 -0700 (MST)

Author: matt
Date: 2008-01-11 01:46:20 -0700 (Fri, 11 Jan 2008)
New Revision: 7401

Modified:
   usrp2/trunk/fpga/eth/rx_prot_engine.v
   usrp2/trunk/fpga/eth/tx_prot_engine.v
Log:
progress.  sending seems to work


Modified: usrp2/trunk/fpga/eth/rx_prot_engine.v
===================================================================
--- usrp2/trunk/fpga/eth/rx_prot_engine.v       2008-01-11 08:44:13 UTC (rev 
7400)
+++ usrp2/trunk/fpga/eth/rx_prot_engine.v       2008-01-11 08:46:20 UTC (rev 
7401)
@@ -26,9 +26,10 @@
      output [15:0] rx_fifo_status,
      output [7:0] rx_seqnum,
      output [7:0] rx_channel,
-     output [7:0] flags
+     output [7:0] rx_flags
      );
 
+   assign        rx_seqnum = 8'hAE;
    wire          read, write, full, empty;
    wire          eop_i, err_i, eop_o, err_o;
    wire [31:0]           dat_i, dat_o;

Modified: usrp2/trunk/fpga/eth/tx_prot_engine.v
===================================================================
--- usrp2/trunk/fpga/eth/tx_prot_engine.v       2008-01-11 08:44:13 UTC (rev 
7400)
+++ usrp2/trunk/fpga/eth/tx_prot_engine.v       2008-01-11 08:46:20 UTC (rev 
7401)
@@ -24,14 +24,15 @@
    input [31:0] set_data,
 
    // Protocol Stuff
-   input [7:0] channel,
+   input [15:0] rx_fifo_status,
    input [7:0] rx_seqnum,
-   input [15:0] rx_fifo_status
+   input [7:0] tx_channel,
+   input [7:0] tx_flags
    );
 
    wire [3:0]  hdr_adr;
    wire [31:0]         hdr_dat;
-   header_ram #(.REGNUM(0),.WIDTH(32)) tx_header_ram
+   header_ram #(.REGNUM(32),.WIDTH(32)) tx_header_ram
      (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .addr(hdr_adr),.q(hdr_dat));
    
@@ -48,7 +49,7 @@
    //  We are allowed to do one more write after we are told the FIFO is full
    //  This allows us to register the _wa signal and speed up timing.
 
-   reg                tx_seqnum;
+   reg [7:0]   tx_seqnum;
    reg                tx_mac_wa_d1;
    always @(posedge clk)
      tx_mac_wa_d1 <= Tx_mac_wa;
@@ -96,7 +97,7 @@
 
    localparam  ETH_TYPE = 16'hBEEF;
    assign      Tx_mac_data = (prot_state == PROT_PKT) ? sfifo_out[31:0] : 
-                            (prot_state == PROT_HDR4) ? 
{ETH_TYPE,channel,tx_seqnum} :
+                            (prot_state == PROT_HDR4) ? 
{ETH_TYPE,tx_channel,tx_seqnum} :
                             (prot_state == PROT_TRAIL) ? 
{rx_fifo_status,8'b0,rx_seqnum} : 
                             hdr_dat;
 





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