[Commit-gnuradio] r7406 - usrp2/trunk/fpga/eth

[matt]

Author: matt
Date: 2008-01-11 19:17:33 -0700 (Fri, 11 Jan 2008)
New Revision: 7406

Modified:
   usrp2/trunk/fpga/eth/rx_prot_engine.v
Log:
receives and buffers packets, checks for correct headers and sequence numbers


Modified: usrp2/trunk/fpga/eth/rx_prot_engine.v
===================================================================
--- usrp2/trunk/fpga/eth/rx_prot_engine.v       2008-01-12 02:16:56 UTC (rev 
7405)
+++ usrp2/trunk/fpga/eth/rx_prot_engine.v       2008-01-12 02:17:33 UTC (rev 
7406)
@@ -18,26 +18,27 @@
      output wr_error_o,
      input wr_ready_i,
      input wr_full_i,
+     output wr_flag_o,
 
      input set_stb,
      input [7:0] set_addr,
      input [31:0] set_data,
      
      output [15:0] rx_fifo_status,
-     output [7:0] rx_seqnum,
-     output [7:0] rx_channel,
+     output reg [7:0] rx_seqnum,
+     output reg [7:0] rx_channel,
      output [7:0] rx_flags
      );
 
-   assign        rx_seqnum = 8'hAE;
    wire          read, write, full, empty;
-   wire          eop_i, err_i, eop_o, err_o;
+   wire          eop_i, err_i, eop_o, err_o, flag_i, sop_i, flag_o, sop_o;
    wire [31:0]           dat_i, dat_o;
    reg                   xfer_active;
 
    wire [3:0]    hdr_adr;
    wire [31:0]           hdr_dat;
-   header_ram #(.REGNUM(0),.WIDTH(32)) rx_header_ram
+   
+   header_ram #(.REGNUM(48),.WIDTH(32)) rx_header_ram
      (.clk(clk),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .addr(hdr_adr),.q(hdr_dat));
 
@@ -57,10 +58,10 @@
    assign read = wr_write_o;
 
    // FIFO in the middle
-   cascadefifo2 #(.WIDTH(34),.SIZE(11)) rx_prot_fifo
+   cascadefifo2 #(.WIDTH(36),.SIZE(11)) rx_prot_fifo
      (.clk(clk),.rst(rst),
-      .datain({eop_i,err_i,dat_i}),.write(write),.full(full),
-      .dataout({eop_o,err_o,dat_o}),.read(read),.empty(empty),
+      .datain({flag_i,sop_i,eop_i,err_i,dat_i}),.write(write),.full(full),
+      .dataout({flag_o,sop_o,eop_o,err_o,dat_o}),.read(read),.empty(empty),
       .clear(0),.fifo_space(rx_fifo_status));
 
    // MAC side
@@ -74,21 +75,75 @@
    localparam PROT_HDR4 = 4;
    localparam PROT_PKT = 5;
 
-   // Things to control: eop_i, err_i, dat_i, write, Rx_mac_rd
-   // Inputs to SM: Rx_mac_sop_i, Rx_mac_eop_i, Rx_mac_ra, Rx_mac_pa, 
+   // Things to control: flag_i, sop_i, eop_i, err_i, dat_i, write, Rx_mac_rd
+   // Inputs to SM: Rx_mac_sop, Rx_mac_eop, Rx_mac_ra, Rx_mac_pa, 
    //                Rx_mac_BE, Rx_mac_err, full
+
+   reg               flag;
+   assign     dat_i = Rx_mac_data;
+   assign     sop_i = Rx_mac_sop;
+   assign     eop_i = Rx_mac_eop;
+   assign     err_i = Rx_mac_err;
+   assign     flag_i = flag;
+   assign     wr_flag_o = flag_o;
+   assign     Rx_mac_rd = (prot_state != PROT_IDLE) && (~full|~Rx_mac_pa);
+   assign     write = (prot_state != PROT_IDLE) && ~full && Rx_mac_pa;       
+
+   assign     hdr_adr = {1'b0,prot_state[2:0]};
+
    always @(posedge clk)
      if(rst)
-       prot_state <= PROT_IDLE;
-     else
+       begin
+         prot_state <= PROT_IDLE;
+         flag = 0;
+       end
+     else if(prot_state == PROT_IDLE)
+       begin
+         flag <= 0;
+         if(Rx_mac_ra)
+           prot_state <= PROT_HDR1;
+       end
+     else if(write)
        case(prot_state)
-        PROT_IDLE : ;
-        PROT_HDR1 : ;
-        PROT_HDR2 : ;
-        PROT_HDR3 : ;
-        PROT_HDR4 : ;
-        PROT_PKT : ;
+        PROT_HDR1 : 
+          begin
+             prot_state <= PROT_HDR2;
+             if(hdr_dat != Rx_mac_data)
+               flag <= 1;
+          end
+        PROT_HDR2 :
+          begin
+             prot_state <= PROT_HDR3;
+             if(hdr_dat != Rx_mac_data)
+               flag <= 1;
+          end
+        PROT_HDR3 :
+          begin
+             prot_state <= PROT_HDR4;
+             if(hdr_dat != Rx_mac_data)
+               flag <= 1;
+          end
+        PROT_HDR4 : 
+          begin
+             prot_state <= PROT_PKT;
+             if(hdr_dat[31:16] != ETH_TYPE)
+               flag <= 1;
+             if(hdr_dat[7:0] != rx_seqnum)
+               flag <= 1;
+             rx_channel <= hdr_dat[15:8];
+          end
+        PROT_PKT : 
+          if(Rx_mac_eop | Rx_mac_err)
+            prot_state <= PROT_IDLE;
        endcase // case(prot_state)
    
+   always @(posedge clk)
+     if(rst)
+       rx_seqnum <= 8'hFF;
+     else if(set_stb & (set_addr == 52))
+       rx_seqnum <= set_data[7:0];
+     else if(write & (prot_state == PROT_HDR4))
+       rx_seqnum <= rx_seqnum + 1;
+   
    // Error cases -- Rx_mac_error, BE != 0, bad_seqno
 endmodule // rx_prot_engine