[Commit-gnuradio] r7407 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx

[matt]

Author: matt
Date: 2008-01-11 20:18:40 -0700 (Fri, 11 Jan 2008)
New Revision: 7407

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
Log:
remove vestigial crap


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-01-12 02:17:33 UTC 
(rev 7406)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-01-12 03:18:40 UTC 
(rev 7407)
@@ -163,26 +163,6 @@
 wire[TX_FF_DEPTH-1:0]                  Add_wr_pluse_pluse;
 reg [TX_FF_DEPTH-1:TX_FF_DEPTH-5] Add_rd_reg_dl1;
 
-`ifdef MAC_TARGET_ALTERA
-
-reg [3:0]       Current_state_MAC           /* synthesis syn_preserve =1 */ ;  
 
-reg [3:0]       Current_state_MAC_reg       /* synthesis syn_preserve =1 */ ;  
   
-reg [3:0]       Current_state_SYS   /* synthesis syn_preserve =1 */;
-reg             Full            /* synthesis syn_keep=1 */;
-reg             AlmostFull      /* synthesis syn_keep=1 */;
-reg             Empty           /* synthesis syn_keep=1 */;
-reg [35:0]      Dout_reg                /* synthesis syn_preserve=1 */;
-reg             Packet_number_sub_edge  /* synthesis syn_preserve=1 */;
-reg             Packet_number_add       /* synthesis syn_preserve=1 */;
-reg             Fifo_ra                 /* synthesis syn_keep=1 */;
-reg             Fifo_data_err_empty     /* synthesis syn_preserve=1 */;
-reg [5:0]       Packet_number_inFF      /* synthesis syn_keep=1 */;   
-reg [5:0]       Packet_number_inFF_reg  /* synthesis syn_preserve=1 */;
-reg         Dout_reg_en /* synthesis syn_keep=1 */;
-reg Add_rd_add /* synthesis syn_keep=1 */;
-
-`else
-
 reg [3:0]       Current_state_MAC;
 reg [3:0]       Current_state_MAC_reg;
 reg [3:0]       Current_state_SYS;
@@ -199,7 +179,6 @@
 reg             Dout_reg_en;
 reg             Add_rd_add;
 
-`endif
 
 reg             Tx_mac_wa           ;
 reg             Tx_mac_wr_dl1           ;
@@ -333,8 +312,6 @@
          Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
       end
 
-//
-
 always @ (posedge Clk_SYS or posedge Reset)
     if (Reset)
         Add_rd_gray_dl1         <=0;
@@ -381,8 +358,6 @@
     else if (Wr_en&&!Full)
         Add_wr  <= Add_wr +1;
         
-        
-//
 always @ (posedge Clk_SYS or posedge Reset)
     if (Reset)
         begin
@@ -485,34 +460,6 @@
         Tx_mac_wa   <=1;
 
 
//******************************************************************************
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-//******************************************************************************
 //rd data to from FF .
 //domain Clk_MAC
 
//******************************************************************************