[Commit-gnuradio] r8592 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-06-16 14:48:02 -0600 (Mon, 16 Jun 2008)
New Revision: 8592

Modified:
   usrp2/trunk/fpga/sdr_lib/rx_dcoffset.v
Log:
working DC offset


Modified: usrp2/trunk/fpga/sdr_lib/rx_dcoffset.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/rx_dcoffset.v      2008-06-15 04:00:18 UTC (rev 
8591)
+++ usrp2/trunk/fpga/sdr_lib/rx_dcoffset.v      2008-06-16 20:48:02 UTC (rev 
8592)
@@ -1,22 +1,34 @@
 
 
-module rx_dcoffset (input clock, input enable, input reset, 
-                   input signed [15:0] adc_in, output signed [15:0] adc_out,
-                   input wire [6:0] serial_addr, input wire [31:0] 
serial_data, input serial_strobe);
-   parameter             MYADDR = 0;
+module rx_dcoffset 
+  #(parameter WIDTH=14,
+    parameter ADDR=8'd0)
+    (input clk, input rst, 
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out);
+
+   // Because of some extra delays to make timing easier, the transfer 
function is:
+   //     (z-1)/(z^2-z-alpha)  where alpha is 1/2^n
    
-   reg signed [31:0]            integrator;
-   wire signed [15:0]           scaled_integrator = integrator[31:16] + 
(integrator[31] & |integrator[15:0]);
-   assign                       adc_out = adc_in - scaled_integrator;
-
-   // FIXME do we need signed?
-   //FIXME  What do we do when clipping?
-   always @(posedge clock)
-     if(reset)
+   wire               set_now = set_stb & (ADDR == set_addr);
+   
+   wire               fixed;  // uses fixed offset
+   wire               signed [WIDTH-1:0] fixed_dco;
+   reg                        signed [31:0] integrator;
+   
+   always @(posedge clk)
+     if(rst)
        integrator <= #1 32'd0;
-     else if(serial_strobe & (MYADDR == serial_addr))
-       integrator <= #1 {serial_data[15:0],16'd0};
-     else if(enable)
+     else if(set_now)
+       integrator <= #1 {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}};
+     else if(~fixed)
        integrator <= #1 integrator + adc_out;
+   
+   wire [WIDTH:0]      scaled_integrator = 
{integrator[31],(integrator[31:32-WIDTH] + (integrator[31] & 
|integrator[31-WIDTH:0]))};
+   wire [WIDTH:0]      adc_out_int = {adc_in[WIDTH-1],adc_in} - 
scaled_integrator;
 
+   clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc
+     (.clk(clk),.in(adc_out_int),.out(adc_out));
+   
+
 endmodule // rx_dcoffset