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[Commit-gnuradio] r8593 - usrp2/trunk/fpga/sdr_lib


From: matt
Subject: [Commit-gnuradio] r8593 - usrp2/trunk/fpga/sdr_lib
Date: Mon, 16 Jun 2008 14:48:56 -0600 (MDT)

Author: matt
Date: 2008-06-16 14:48:55 -0600 (Mon, 16 Jun 2008)
New Revision: 8593

Modified:
   usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v
Log:
now includes DC offset correction


Modified: usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v      2008-06-16 20:48:02 UTC (rev 
8592)
+++ usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v      2008-06-16 20:48:55 UTC (rev 
8593)
@@ -14,6 +14,7 @@
    );
 
    wire [15:0] scale_i, scale_q;
+   wire [13:0] adc_a_ofs, adc_b_ofs;
    wire [31:0] phase_inc;
    reg [31:0]  phase;
 
@@ -41,6 +42,14 @@
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+     
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_a),.adc_out(adc_a_ofs));
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+     
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_b),.adc_out(adc_b_ofs));
+      
    always @(posedge clk)
      if(rst)
        phase <= 0;
@@ -49,7 +58,7 @@
 
    MULT18X18S mult_i
      (.P(prod_i),    // 36-bit multiplier output
-      .A({{4{adc_a[13]}},adc_a} ),    // 18-bit multiplier input
+      .A({{4{adc_a_ofs[13]}},adc_a_ofs} ),    // 18-bit multiplier input
       .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
@@ -58,7 +67,7 @@
 
    MULT18X18S mult_q
      (.P(prod_q),    // 36-bit multiplier output
-      .A({{4{adc_b[13]}},adc_b} ),    // 18-bit multiplier input
+      .A({{4{adc_b_ofs[13]}},adc_b_ofs} ),    // 18-bit multiplier input
       .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input





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