[Commit-gnuradio] r8709 - in usrp2/trunk/fpga: control_lib models

[matt]

Author: matt
Date: 2008-06-25 17:14:56 -0600 (Wed, 25 Jun 2008)
New Revision: 8709

Added:
   usrp2/trunk/fpga/control_lib/simple_uart.v
   usrp2/trunk/fpga/control_lib/simple_uart_tx.v
Modified:
   usrp2/trunk/fpga/models/uart_rx.v
Log:
UART TX replacement.  Appears to be working.


Added: usrp2/trunk/fpga/control_lib/simple_uart.v
===================================================================
--- usrp2/trunk/fpga/control_lib/simple_uart.v                          (rev 0)
+++ usrp2/trunk/fpga/control_lib/simple_uart.v  2008-06-25 23:14:56 UTC (rev 
8709)
@@ -0,0 +1,54 @@
+
+module simple_uart
+  (input clk_i, input rst_i,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+   output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+
+   // Register Map
+   // 0  8 bits   Read -- buffer level, Write -- char to send
+   // 1  16 bits  Clock Divider 
+   // 2           Control Register
+
+   wire   wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire   wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+   wire   tx_fifo_full;
+   assign rx_int_o = 0;
+   
+   reg [15:0] clkdiv;
+   wire [7:0] tx_fifo_level;
+   wire [7:0] rx_fifo_level = 0;
+   reg [31:0] ctrl;
+   always @(posedge clk_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & ~ack_o;
+   
+   always @(posedge clk_i)
+     if (rst_i)
+       begin
+         clkdiv <= 0;
+         ctrl <= 0;
+       end
+     else if (wb_wr)
+       case( adr_i)
+        1 : clkdiv <= dat_i[15:0];
+       endcase // case( adr_i[3:2] )
+   
+   always @(posedge clk_i)
+     case (adr_i)
+       0 : dat_o <= tx_fifo_level;
+       1 : dat_o <= ctrl;
+     endcase // case(adr_i)
+      
+   simple_uart_tx uart_tx
+     (.clk(clk_i),.rst(rst_i),
+      .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == 0)),
+      .fifo_level(tx_fifo_level),.fifo_full(tx_fifo_full),
+      .clkdiv(clkdiv),.baudclk(baud_o),.tx(tx_o));
+     
+   assign tx_int_o = ~tx_fifo_full;   
+   
+endmodule // simple_uart

Added: usrp2/trunk/fpga/control_lib/simple_uart_tx.v
===================================================================
--- usrp2/trunk/fpga/control_lib/simple_uart_tx.v                               
(rev 0)
+++ usrp2/trunk/fpga/control_lib/simple_uart_tx.v       2008-06-25 23:14:56 UTC 
(rev 8709)
@@ -0,0 +1,60 @@
+
+module simple_uart_tx
+  (input clk, input rst, 
+   input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output 
fifo_full, 
+   input [15:0] clkdiv, output baudclk, output reg tx);
+
+   reg [15:0]  baud_ctr;
+   reg [3:0]   bit_ctr;
+
+   wire        read, empty;
+   wire [7:0]  char_to_send;
+   
+   shortfifo #(.WIDTH(8)) fifo
+     (.clk(clk),.rst(rst),
+      .datain(fifo_in),.write(fifo_write),.full(fifo_full),
+      .dataout(char_to_send),.read(read),.empty(empty),
+      .clear(0),.space(fifo_level[3:0]));
+   assign      fifo_level[7:4] = 0;
+   
+   always @(posedge clk)
+     if(rst)
+       baud_ctr <= 0;
+     else if (baud_ctr >= clkdiv)
+       baud_ctr <= 0;
+     else
+       baud_ctr <= baud_ctr + 1;
+
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else if(baud_ctr == clkdiv)
+       if(bit_ctr == 9)
+        bit_ctr <= 0;
+       else if(bit_ctr != 0)
+        bit_ctr <= bit_ctr + 1;
+       else if(~empty)
+        bit_ctr <= 1;
+   
+   always @(posedge clk)
+     if(rst)
+       tx <= 1;
+     else
+       case(bit_ctr)
+        0 : tx <= 1;
+        1 : tx <= 0;
+        2 : tx <= char_to_send[0];
+        3 : tx <= char_to_send[1];
+        4 : tx <= char_to_send[2];
+        5 : tx <= char_to_send[3];
+        6 : tx <= char_to_send[4];
+        7 : tx <= char_to_send[5];
+        8 : tx <= char_to_send[6];
+        9 : tx <= char_to_send[7];
+        default : tx <= 1;
+       endcase // case(bit_ctr)
+
+   assign      read = (bit_ctr == 9) && (baud_ctr == clkdiv);
+   assign      baudclk = (baud_ctr == 1);  // Only for debug purposes
+   
+endmodule // simple_uart_tx

Modified: usrp2/trunk/fpga/models/uart_rx.v
===================================================================
--- usrp2/trunk/fpga/models/uart_rx.v   2008-06-25 21:24:03 UTC (rev 8708)
+++ usrp2/trunk/fpga/models/uart_rx.v   2008-06-25 23:14:56 UTC (rev 8709)
@@ -6,8 +6,9 @@
 module uart_rx (input baudclk, input rxd);
    reg [8:0] sr = 9'b0;
    reg [3:0]  baud_ctr = 4'b0;
+
+   /*
    wire       byteclk = baud_ctr[3];
-
    reg               rxd_d1 = 0;
    always @(posedge baudclk)
      rxd_d1 <= rxd;
@@ -17,7 +18,10 @@
        baud_ctr <= 0;
      else
        baud_ctr <= baud_ctr + 1;
+*/
 
+   wire       byteclk = baudclk;
+   
    always @(posedge byteclk)
      sr <= { rxd, sr[8:1] };
 
@@ -39,6 +43,6 @@
        default :
         state <= 0;
      endcase // case(state)
-   
+
 endmodule // uart_rx