[Commit-gnuradio] r8710 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-06-25 17:15:55 -0600 (Wed, 25 Jun 2008)
New Revision: 8710

Modified:
   usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v
Log:
muxing for ADC buses so we can swap I/Q, or ignore one for real signals


Modified: usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v      2008-06-25 23:14:56 UTC (rev 
8709)
+++ usrp2/trunk/fpga/sdr_lib/dsp_core_rx.v      2008-06-25 23:15:55 UTC (rev 
8710)
@@ -15,6 +15,7 @@
 
    wire [15:0] scale_i, scale_q;
    wire [13:0] adc_a_ofs, adc_b_ofs;
+   reg [13:0] adc_i, adc_q;
    wire [31:0] phase_inc;
    reg [31:0]  phase;
 
@@ -49,8 +50,29 @@
    rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
      
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_in(adc_b),.adc_out(adc_b_ofs));
-      
+
+   wire [3:0]  muxctrl;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+
    always @(posedge clk)
+     case(muxctrl[1:0])
+       0: adc_i <= adc_a_ofs;
+       1: adc_i <= adc_b_ofs;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case(muxctrl[1:0])
+          
+   always @(posedge clk)
+     case(muxctrl[3:2])
+       0: adc_q <= adc_b_ofs;
+       1: adc_q <= adc_a_ofs;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case(muxctrl[3:2])
+       
+   always @(posedge clk)
      if(rst)
        phase <= 0;
      else if(run)
@@ -58,7 +80,7 @@
 
    MULT18X18S mult_i
      (.P(prod_i),    // 36-bit multiplier output
-      .A({{4{adc_a_ofs[13]}},adc_a_ofs} ),    // 18-bit multiplier input
+      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
       .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input
@@ -67,7 +89,7 @@
 
    MULT18X18S mult_q
      (.P(prod_q),    // 36-bit multiplier output
-      .A({{4{adc_b_ofs[13]}},adc_b_ofs} ),    // 18-bit multiplier input
+      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
       .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
       .C(clk),    // Clock input
       .CE(1),  // Clock enable input