[Commit-gnuradio] r8846 - usrp2/trunk/fpga/top/u2_rev3

[matt]

Author: matt
Date: 2008-07-09 13:04:15 -0600 (Wed, 09 Jul 2008)
New Revision: 8846

Modified:
   usrp2/trunk/fpga/top/u2_rev3/u2_rev3.ucf
   usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v
Log:
moved GMII_RX_CLK to a real clock pin, moved PPS_IN to a 3.3V pin, moved around 
LEDs and added a new one, and added watchdog pins POR and WDI


Modified: usrp2/trunk/fpga/top/u2_rev3/u2_rev3.ucf
===================================================================
--- usrp2/trunk/fpga/top/u2_rev3/u2_rev3.ucf    2008-07-09 19:02:02 UTC (rev 
8845)
+++ usrp2/trunk/fpga/top/u2_rev3/u2_rev3.ucf    2008-07-09 19:04:15 UTC (rev 
8846)
@@ -1,8 +1,9 @@
-NET "leds[0]"  LOC = "F7"  ; 
-NET "leds[1]"  LOC = "E5"  ; 
-NET "leds[2]"  LOC = "B7"  ; 
-NET "leds[3]"  LOC = "C11"  ; 
-NET "leds[4]"  LOC = "AB19"  ;
+NET "leds[0]"  LOC = "E8"  ; 
+NET "leds[1]"  LOC = "F7"  ; 
+NET "leds[2]"  LOC = "E5"  ; 
+NET "leds[3]"  LOC = "B7"  ; 
+NET "leds[4]"  LOC = "C11"  ;
+NET "leds[5]"  LOC = "AB19"  ;
 NET "debug[0]"  LOC = "N5"  ;
 NET "debug[1]"  LOC = "N6"  ;
 NET "debug[2]"  LOC = "P1"  ;
@@ -65,7 +66,7 @@
 NET "GMII_RXD[5]"  LOC = "V13"  ;
 NET "GMII_RXD[6]"  LOC = "Y13"  ;
 NET "GMII_RXD[7]"  LOC = "AA13"  ;
-NET "GMII_RX_CLK"  LOC = "W16"  ; 
+NET "GMII_RX_CLK"  LOC = "AA12"  ; 
 NET "GMII_RX_DV"  LOC = "AB16"  ; 
 NET "GMII_RX_ER"  LOC = "AA16"  ; 
 NET "MDIO"  LOC = "Y16" |PULLUP ; 
@@ -166,6 +167,8 @@
 NET "cpld_detached"  LOC = "V11"  ;
 NET "cpld_init_b"  LOC = "W12"  ;
 NET "cpld_misc"  LOC = "Y12"  ;
+NET "POR"  LOC = "W18"  ;
+NET "WDI"  LOC = "W15"  ;
 NET "adc_a[0]"  LOC = "A14" | IOBDELAY= "NONE" ;
 NET "adc_a[1]"  LOC = "B14" | IOBDELAY= "NONE" ;
 NET "adc_a[2]"  LOC = "C13" | IOBDELAY= "NONE" ;
@@ -244,7 +247,7 @@
 NET "clk_fpga_p"  LOC = "A11"  ; 
 NET "clk_fpga_n"  LOC = "B11"  ; 
 NET "clk_to_mac"  LOC = "AB12"  ; 
-NET "pps_in"  LOC = "Y11"  ; 
+NET "pps_in"  LOC = "K1"  ; 
 NET "sclk"  LOC = "K5"  ; 
 NET "sen_clk"  LOC = "K6"  ; 
 NET "sen_dac"  LOC = "L1"  ; 

Modified: usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v
===================================================================
--- usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v      2008-07-09 19:02:02 UTC (rev 
8845)
+++ usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v      2008-07-09 19:04:15 UTC (rev 
8846)
@@ -1,10 +1,10 @@
 `timescale 1ns / 1ps
 
//////////////////////////////////////////////////////////////////////////////////
 
-module u2_rev2
+module u2_rev3
   (
    // Misc, debug
-   output [4:0] leds,
+   output [5:0] leds,
    output [31:0] debug,
    output [1:0] debug_clk,
    output uart_tx_o,
@@ -76,6 +76,10 @@
    input cpld_detached,// V11 unused
    output cpld_init_b,  // W12 unused dual purpose
    input cpld_misc,  // Y12 unused
+
+   // Watchdog interface
+   input POR,
+   output WDI,
    
    // ADC
    input [13:0] adc_a,
@@ -240,8 +244,8 @@
    IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
 
    // LEDs are active low outputs
-   wire [4:0] leds_int;
-   assign     leds = 5'b01111 ^ leds_int;  // all except eth are active-low
+   wire [5:0] leds_int;
+   assign     leds = 6'b011111 ^ leds_int;  // all except eth are active-low
    
    // SPI
    wire        miso, mosi, sclk_int;