[Commit-gnuradio] r8847 - usrp2/trunk/fpga/top/u2_rev3

[matt]

Author: matt
Date: 2008-07-09 15:33:39 -0600 (Wed, 09 Jul 2008)
New Revision: 8847

Modified:
   usrp2/trunk/fpga/top/u2_rev3/Makefile
   usrp2/trunk/fpga/top/u2_rev3/u2_rev3.ucf
   usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v
Log:
remove old constraints, make everything compile


Modified: usrp2/trunk/fpga/top/u2_rev3/Makefile
===================================================================
--- usrp2/trunk/fpga/top/u2_rev3/Makefile       2008-07-09 19:04:15 UTC (rev 
8846)
+++ usrp2/trunk/fpga/top/u2_rev3/Makefile       2008-07-09 21:33:39 UTC (rev 
8847)
@@ -29,7 +29,7 @@
 # Project Setup
 ##################################################
 BUILD_DIR := $(shell pwd)/build/
-export TOP_MODULE := u2_rev2
+export TOP_MODULE := u2_rev3
 export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
 
 ##################################################
@@ -169,8 +169,8 @@
 timing/time_sync.v \
 timing/timer.v \
 top/u2_core/u2_core.v \
-top/u2_rev2/u2_rev2.ucf \
-top/u2_rev2/u2_rev2.v 
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v 
 
 ##################################################
 # Process Properties

Modified: usrp2/trunk/fpga/top/u2_rev3/u2_rev3.ucf
===================================================================
--- usrp2/trunk/fpga/top/u2_rev3/u2_rev3.ucf    2008-07-09 19:04:15 UTC (rev 
8846)
+++ usrp2/trunk/fpga/top/u2_rev3/u2_rev3.ucf    2008-07-09 21:33:39 UTC (rev 
8847)
@@ -311,9 +311,6 @@
 NET "clk_to_mac" TNM_NET = "clk_to_mac";
 TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
 
-#NET "dsp_clk" TNM_NET = "dsp_clk";
-#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
-
 NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
 TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
 
@@ -326,10 +323,6 @@
 NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
 TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
 
-#NET "wb_clk" TNM_NET = "wb_clk";
-#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %;
-
-NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
 NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
 
 #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;

Modified: usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v
===================================================================
--- usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v      2008-07-09 19:04:15 UTC (rev 
8846)
+++ usrp2/trunk/fpga/top/u2_rev3/u2_rev3.v      2008-07-09 21:33:39 UTC (rev 
8847)
@@ -155,6 +155,8 @@
    inout [15:0] io_rx   
    );
 
+   assign      WDI = 0;
+   
    assign      cpld_init_b = 0;
    // FPGA-specific pins connections
    wire        clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;