[Commit-gnuradio] r9094 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-07-31 20:19:07 -0600 (Thu, 31 Jul 2008)
New Revision: 9094

Modified:
   usrp2/trunk/fpga/control_lib/cascadefifo.v
   usrp2/trunk/fpga/control_lib/cascadefifo2.v
Log:
interface changes for the new uniform style of occupied/space nets


Modified: usrp2/trunk/fpga/control_lib/cascadefifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/cascadefifo.v  2008-08-01 02:18:26 UTC (rev 
9093)
+++ usrp2/trunk/fpga/control_lib/cascadefifo.v  2008-08-01 02:19:07 UTC (rev 
9094)
@@ -19,24 +19,31 @@
      input clear,
      output full,
      output empty,
-     output [15:0] fifo_space);
+     output [15:0] space,
+     output [15:0] occupied);
 
    wire [WIDTH-1:0] data_int;
    wire            empty_int, full_int, transfer;
+   wire [4:0]      short_space, short_occupied;
+   wire [15:0]             long_space, long_occupied;
    
    shortfifo #(.WIDTH(WIDTH)) shortfifo
      (.clk(clk),.rst(rst),.clear(clear),
       .datain(datain), .write(write), .full(full),
-      .dataout(data_int), .read(transfer), .empty(empty_int) );
+      .dataout(data_int), .read(transfer), .empty(empty_int),
+      .space(short_space),.occupied(short_occupied) );
 
    longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
      (.clk(clk),.rst(rst),.clear(clear),
       .datain(data_int), .write(transfer), .full(full_int),
       .dataout(dataout), .read(read), .empty(empty),
-      .fifo_space(fifo_space) );
+      .space(long_space),.occupied(long_occupied) );
 
    assign          transfer = ~empty_int & ~full_int;      
 
+   assign          space = {11'b0,short_space} + long_space;
+   assign          occupied = {11'b0,short_occupied} + long_occupied;
+   
 endmodule // cascadefifo
 
 

Modified: usrp2/trunk/fpga/control_lib/cascadefifo2.v
===================================================================
--- usrp2/trunk/fpga/control_lib/cascadefifo2.v 2008-08-01 02:18:26 UTC (rev 
9093)
+++ usrp2/trunk/fpga/control_lib/cascadefifo2.v 2008-08-01 02:19:07 UTC (rev 
9094)
@@ -16,31 +16,39 @@
      input clear,
      output full,
      output empty,
-     output [15:0] fifo_space);
+     output [15:0] space,
+     output [15:0] occupied);
 
    wire [WIDTH-1:0] data_int, data_int2;
    wire            empty_int, full_int, transfer;
    wire            empty_int2, full_int2, transfer2;
+   wire [4:0]      s1_space, s1_occupied, s2_space, s2_occupied;
+   wire [15:0]             l_space, l_occupied;
    
    shortfifo #(.WIDTH(WIDTH)) shortfifo
      (.clk(clk),.rst(rst),.clear(clear),
       .datain(datain), .write(write), .full(full),
-      .dataout(data_int), .read(transfer), .empty(empty_int) );
-
+      .dataout(data_int), .read(transfer), .empty(empty_int),
+      .space(s1_space),.occupied(s1_occupied) );
+      
    longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
      (.clk(clk),.rst(rst),.clear(clear),
       .datain(data_int), .write(transfer), .full(full_int),
       .dataout(data_int2), .read(transfer2), .empty(empty_int2),
-      .fifo_space(fifo_space) );
-
+      .space(l_space),.occupied(l_occupied) );
+   
    shortfifo #(.WIDTH(WIDTH)) shortfifo2
      (.clk(clk),.rst(rst),.clear(clear),
       .datain(data_int2), .write(transfer2), .full(full_int2),
-      .dataout(dataout), .read(read), .empty(empty) );
-
+      .dataout(dataout), .read(read), .empty(empty),
+      .space(s2_space),.occupied(s2_occupied) );
+   
    assign          transfer = ~empty_int & ~full_int;      
    assign          transfer2 = ~empty_int2 & ~full_int2;           
-
+   
+   assign          space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
+   assign          occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + 
l_occupied;
+      
 endmodule // cascadefifo2