[Commit-gnuradio] r9098 - usrp2/trunk/fpga/eth

[matt]

Author: matt
Date: 2008-07-31 20:26:42 -0600 (Thu, 31 Jul 2008)
New Revision: 9098

Modified:
   usrp2/trunk/fpga/eth/mac_txfifo_int.v
Log:
pass fifo information to the outside


Modified: usrp2/trunk/fpga/eth/mac_txfifo_int.v
===================================================================
--- usrp2/trunk/fpga/eth/mac_txfifo_int.v       2008-08-01 02:25:41 UTC (rev 
9097)
+++ usrp2/trunk/fpga/eth/mac_txfifo_int.v       2008-08-01 02:26:42 UTC (rev 
9098)
@@ -16,8 +16,13 @@
    output rd_done_o,
    output rd_error_o,
    input rd_sop_i,
-   input rd_eop_i);
+   input rd_eop_i,
 
+   // FIFO Status
+   output [15:0] fifo_occupied,
+   output fifo_full,
+   output fifo_empty  );
+
    wire  empty, full, sfifo_write, sfifo_read;
    wire [33:0] sfifo_in, sfifo_out;
 
@@ -29,8 +34,11 @@
     */
    fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
      (.rst(rst),
-      .wr_clk(clk),.din({2'b0,sfifo_in}),.full(full),.wr_en(sfifo_write),
-      .rd_clk(mac_clk),.dout(sfifo_out),.empty(empty),.rd_en(sfifo_read));
+      
.wr_clk(clk),.din({2'b0,sfifo_in}),.full(full),.wr_en(sfifo_write),.wr_data_count(fifo_occupied[8:0]),
+      
.rd_clk(mac_clk),.dout(sfifo_out),.empty(empty),.rd_en(sfifo_read),.rd_data_count()
 );
+   assign      fifo_occupied[15:9] = 0;
+   assign      fifo_full = full;
+   assign      fifo_empty = empty;   // Note empty is in wrong clock domain
    
    // MAC side signals
    //  We are allowed to do one more write after we are told the FIFO is full
@@ -67,5 +75,3 @@
    assign      rd_error_o = 0;  // No possible error situations?
    
 endmodule // mac_txfifo_int
-
-