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[Commit-gnuradio] r9580 - in gnuradio/branches/developers/ets/inband/usr
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From: |
ets |
|
Subject: |
[Commit-gnuradio] r9580 - in gnuradio/branches/developers/ets/inband/usrp/fpga: inband_lib inband_lib/tb toplevel/usrp_inband_usb |
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Date: |
Mon, 15 Sep 2008 09:54:41 -0600 (MDT) |
Author: ets
Date: 2008-09-15 09:54:38 -0600 (Mon, 15 Sep 2008)
New Revision: 9580
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_packetizer_a.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_packetizer_b.v
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
Log:
- moved chan buffer logic into packetizer module
- moved IQ interleaving into packetizer
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-09-15 15:48:31 UTC (rev 9579)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-09-15 15:54:38 UTC (rev 9580)
@@ -141,20 +141,7 @@
assign usbclk_inv = ~usbclk; //invert so all logic is posedge
/////////////////////////////////////////////////////////////////////////
- // IQ interleaving
- reg iq; //select I or Q
- reg rx_wren; //Channel buffer write signal
-
- always @ (posedge rxclk) begin
- if (reset) iq = 1'b0;
- else iq = rx_wren ? ~iq : 1'b0;
-
- rx_wren = ~reset & ( rxstrobe | iq);
- end
-
-
-
/////////////////////////////////////////////////////////////////////////
- //overrun signal
+ // FX2 overrun signal
wire [NUM_CHAN:0] overrun;
always @ (posedge usbclk_inv) begin
@@ -193,13 +180,20 @@
// Generate the data channel buffers
// select the data inputs for each channel
- wire [15:0] i_chan_data[4:0];
+ wire [15:0] i_chan_data_i[4:0];
+ wire [15:0] i_chan_data_q[4:0];
- assign i_chan_data[0] = rx_databus; //control data
- assign i_chan_data[1] = iq ? ch_1 : ch_0;
- assign i_chan_data[2] = iq ? ch_3 : ch_2;
- assign i_chan_data[3] = iq ? ch_5 : ch_4;
- assign i_chan_data[4] = iq ? ch_7 : ch_6;
+ assign i_chan_data_i[0] = rx_databus; //control data
+ assign i_chan_data_q[0] = 16'h0000;
+ assign i_chan_data_i[1] = ch_0;
+ assign i_chan_data_q[1] = ch_1;
+ assign i_chan_data_i[2] = ch_2;
+ assign i_chan_data_q[2] = ch_3;
+ assign i_chan_data_i[3] = ch_4;
+ assign i_chan_data_q[3] = ch_5;
+ assign i_chan_data_i[4] = ch_6;
+ assign i_chan_data_q[4] = ch_7;
+
wire [5:0] i_rssi[4:0];
assign i_rssi[0] = rssi_0[5:0];
@@ -219,6 +213,7 @@
wire chan_rd;
//declare nets to be assigned by generate below
+ wire interleaved[NUM_CHAN:0];
wire i_wren[NUM_CHAN:0];
wire i_flush[NUM_CHAN:0];
@@ -250,6 +245,7 @@
//the control channel (0) is connected differently
//TODO: maybe this should be broken out for clarity
if (i == 0) begin
+ assign interleaved[i] = 0;
assign i_wren[i] = rx_WR;
assign i_flush[i] = cmd_flush;
assign i_header_data[i][`CB_CHAN] = 5'h1f;
@@ -257,8 +253,9 @@
assign i_header_data[i][`CB_UNDERRUN] = 1'b0;
end
else begin
- assign i_wren[i] = rx_wren;
- assign i_flush[i] = 1'd0;
+ assign interleaved[i] = 1;
+ assign i_wren[i] = rxstrobe;
+ assign i_flush[i] = 0;
assign i_header_data[i][`CB_CHAN] = i-1;
assign i_header_data[i][`CB_RSSI] = i_rssi[i-1];
assign i_header_data[i][`CB_UNDERRUN] =
tx_underrun[i-1];
@@ -280,7 +277,8 @@
.reset ( reset
),
.wrclk ( rxclk
),
- .wren ( i_wren[i]
),
+ .interleaved ( interleaved[i]
),
+ .wren ( i_wren[i]
),
.flush_packet ( i_flush[i]
),
.rdclk ( usbclk_inv
),
@@ -290,7 +288,8 @@
.packet_rdy ( chans_ready[i]
),
.overrun ( overrun[i]
),
- .i_chan_data ( i_chan_data[i]
),
+ .i_chan_data_i ( i_chan_data_i[i]
),
+ .i_chan_data_q ( i_chan_data_q[i]
),
.i_header_data ( i_header_data[i]
),
.o_chan_data ( o_chan_data[i]
),
.o_header_data ( o_header_data[i]
)
@@ -369,8 +368,8 @@
assign debugbus = 16'h0;
//IQ interleaving
- assign dbg_rx_wren = rx_wren;
- assign dbg_iq = iq;
+ assign dbg_rx_wren = 0;
+ assign dbg_iq = 0;
//chan buffer
assign dbg_sample_counter_0 = dbg_sample_counter[0];
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
2008-09-15 15:48:31 UTC (rev 9579)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_channel_buffer.v
2008-09-15 15:54:38 UTC (rev 9580)
@@ -3,6 +3,9 @@
// including timestamp/header sampling and variable payload
// length packet generation.
//
+// The actual logic is encapsulated in rx_packetizer, this
+// module simply joins that logic to the fifos.
+//
// Header information such as timestamp is saved in a seperate
// FIFO that runs parallel to the channel data FIFO.
//
@@ -12,11 +15,11 @@
// to know the size at the time of the first sample. This is
// used for the control channel and in overrun conditions.
//
-// NOTE: The FIFOS used are dual clock, WITH look ahead, so
-// rd_req is asserted AFTER the read (it is an ACK). This
-// helps us with the FX2 RD/usbdata timing.
+// NOTE: Both FIFOS used are dual clock WITH look ahead, so
+// rd_req is asserted AFTER the read (it is an ACK).
//
// Dependencies:
+// rx_packetizer_[a/b].v
// inband_packet_defs.v
// dcfifo_generic.v
@@ -32,11 +35,13 @@
//Input control
input wrclk,
input wren,
+ input interleaved, //IQ or not
input flush_packet, //will send non-full packet
//Input
- input [15:0] i_chan_data,
input [63:0] i_header_data,
+ input [15:0] i_chan_data_i,
+ input [15:0] i_chan_data_q,
//Output control
input rdclk, //negedge
@@ -46,7 +51,7 @@
//Status
output [6:0] num_packets, //Number of packets ready to go
output packet_rdy,
- output reg overrun,
+ output overrun,
//Output
output [15:0] o_chan_data,
@@ -60,16 +65,15 @@
,output dbg_cd_full
,output dbg_save_header
);
-
- parameter SAMP_PER_PKT = 252; //16 bit samples
-
+ assign packet_rdy = num_packets ? 1'b1 : 1'b0;
- // Temporary header info, prior to being pushed to fifo
- reg [63:0] temp_header;
-
// Packet header fifo related
+ wire [63:0] fifo_header;
+ wire [15:0] fifo_chan_data;
+
wire ph_full;
+ wire ph_wren;
dcfifo_generic #(
.WIDTH ( 64 ),
@@ -80,9 +84,9 @@
ph_fifo (
.aclr ( reset ),
// .data ( ph_fifo_input ),
- .data ( temp_header ),
+ .data ( fifo_header ),
.wrclk ( wrclk ),
- .wrreq ( save_header ),
+ .wrreq ( ph_wren ),
.wrfull ( ph_full ),
.rdclk ( rdclk ),
.rdreq ( rd_header_en ),
@@ -96,6 +100,7 @@
//Channel data fifo related
wire [CD_FIFO_SZ_L2-1:0] cd_wrusedw;
wire cd_full;
+ wire cd_wren;
dcfifo_generic #(
.WIDTH ( 16 ),
@@ -105,9 +110,9 @@
)
cd_fifo (
.aclr ( reset ),
- .data ( i_chan_data ),
+ .data ( fifo_chan_data ),
.wrclk ( wrclk ),
- .wrreq ( wren && !overrun ), //block on overrun
+ .wrreq ( cd_wren ),
.wrfull ( cd_full ),
.wrusedw ( cd_wrusedw ),
.rdclk ( rdclk ),
@@ -117,76 +122,52 @@
//,.rdusedw ( cd_rdusedw )
);
-
/////////////////////////////////////////////////////////////////////////
- // Sampling and overrun logic
- // Keep track of how many samples we have saved so we can save header
- // info at the right time.
- //
- // Overrun behavior is to fill the data fifo until full, at which
- // time the header is pushed with the current payload size and the
- // ovverrun bit set. Sampling is suspended until there is room for
- // a complete packet. If the header fifo is full (unlikely, and which
- // would happen after completing a packet), sampling is suspended.
- // In any case, all samples in a packet should be contiguous.
-
- reg [7:0] sample_counter;
- reg save_header; //temp->fifo on this signal
- reg do_flush; //internal signal to force a packet
-
- always @ ( posedge wrclk ) begin
- if (reset) begin
- save_header <= 1'b0;
- do_flush = 1'b0;
- overrun = 1'b0;
- sample_counter <= 8'd0;
- end
- else begin
- //Overrun logic
- if (ph_full || cd_full) begin
- //only flush header once
- if (!overrun && !ph_full)
- do_flush = 1'b1;
- overrun = 1'b1;
- end
- else if (overrun && !ph_full && (cd_wrusedw <
(CD_FIFO_SIZE - SAMP_PER_PKT)))
- overrun = 1'b0;
+ rx_packetizer_a
+ #(
+ .PH_FIFO_SIZE ( PH_FIFO_SIZE ),
+ .PH_FIFO_SZ_L2 ( PH_FIFO_SZ_L2 ),
+ .CD_FIFO_SIZE ( CD_FIFO_SIZE ),
+ .CD_FIFO_SZ_L2 ( CD_FIFO_SZ_L2 )
+ )
+ packetizer
+ (
+ .reset ( reset ),
+ .clk ( wrclk ),
+ .interleaved ( interleaved ),
+ .wren ( wren ),
+ .flush_packet ( flush_packet ),
+
+ .i_header_data ( i_header_data ),
+ .i_chan_data_i ( i_chan_data_i ),
+ .i_chan_data_q ( i_chan_data_q ),
+
+ //.ph_usedw ( ph_fifo.wrusedw ),
+ .ph_full ( ph_full ),
- if (flush_packet)
- do_flush = 1'b1;
-
- //Only sample on wren
- if (wren && !overrun) begin //new channel data
- //if this is first sample, save the header info
(incl timestamp)
- if (!sample_counter) temp_header <=
i_header_data;
+ .cd_usedw ( cd_wrusedw ),
+ .cd_full ( cd_full ),
+
+ .ph_wren ( ph_wren ),
+ .cd_wren ( cd_wren ),
+ .overrun ( overrun ),
- sample_counter <= sample_counter + 8'd1;
//blocking assign, we want new val now for size
- end
-
- //If done w/ packet (full or flush), then save the
header info to fifo
- if (do_flush || (sample_counter == SAMP_PER_PKT)) begin
- //update some header values before pushing onto
the fifo
- temp_header[`CB_PAYLOAD_LEN] <=
(sample_counter<<1); //actual payload length (x2 bytes)
- temp_header[`CB_OVERRUN] <= overrun;
+ .o_header ( fifo_header ),
+ .o_chan_data ( fifo_chan_data )
+
+ //Debug
+ ,.dbg_sample_counter ( dbg_sample_counter )
+ );
- save_header <= 1'b1; //wren for header fifo
- sample_counter <= 8'd0; //start counting new
packet
- do_flush = 1'b0;
- end
- else
- save_header <= 1'b0;
- end //else
- end //always
- //Ready signal
- assign packet_rdy = num_packets ? 1'b1 : 1'b0;
-
//debug
- assign dbg_sample_counter = sample_counter;
- assign dbg_cd_wrusedw = cd_wrusedw;
- assign dbg_ph_full = ph_full;
- assign dbg_cd_full = cd_full;
- assign dbg_save_header = save_header;
+ //assign dbg_sample_counter = sample_counter;
+ assign dbg_save_header = ph_wren;
+ assign dbg_ph_full = ph_full;
+ assign dbg_cd_wrusedw = cd_wrusedw;
+ assign dbg_cd_full = cd_full;
+
+
endmodule
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_packetizer_a.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_packetizer_a.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_packetizer_a.v
2008-09-15 15:54:38 UTC (rev 9580)
@@ -0,0 +1,150 @@
+// rx_packetizer_a.v
+
+// This version will block and signal an overrun if there is not room
+// for a complete packet.
+
+// Sampling and overrun logic
+// Keep track of how many samples we have saved so we can save header
+// info at the right time.
+
+// In any case, all samples in a packet should be contiguous.
+
+// TODO: handle flush when full
+
+module rx_packetizer_a
+#(
+ parameter PH_FIFO_SIZE = 128, //Depth of header fifo
+ parameter PH_FIFO_SZ_L2 = 7, //log2(SIZE)
+ parameter CD_FIFO_SIZE = 1024, //Depth of channel data fifo
+ parameter CD_FIFO_SZ_L2 = 10
+)(
+ input reset,
+ input clk,
+ input interleaved,
+ input wren,
+ input flush_packet, //will
send non-full packet
+
+ input [63:0] i_header_data,
+ input [15:0] i_chan_data_i,
+ input [15:0] i_chan_data_q,
+
+ input [PH_FIFO_SZ_L2-1:0] ph_usedw,
+ input ph_full,
+
+ input [CD_FIFO_SZ_L2-1:0] cd_usedw,
+ input cd_full,
+
+ output reg ph_wren,
//packet header fifo enable
+ output reg cd_wren,
//channel data fifo enable
+ output reg overrun,
+
+ output reg [63:0] o_header,
+ output reg [15:0] o_chan_data
+
+ //Debug
+ ,output [7:0] dbg_sample_counter
+);
+
+ parameter SAMP_PER_PKT = 252; //16 bit samples
+
+ reg [7:0] sample_counter;
+ reg pause;
+ reg wr_header; //internal signal to save
header to fifo
+ reg wr_data; //internal signal to save data
to fifo
+
+ //for interleaving
+ reg [15:0] temp_i,temp_q;
+
+ always @ ( posedge clk ) begin
+ if (reset) begin
+ sample_counter = 0;
+ overrun = 0;
+ pause = 0;
+ wr_header = 0;
+ ph_wren = 0;
+ wr_data = 0;
+ cd_wren = 0;
+ end
+ else begin
+ //defaults, override later
+ //we need to make sure these are only set for 1 clk,
+ //not wren cycle
+ ph_wren = 0;
+ cd_wren = 0;
+
+ if (wren) begin
+ //Before starting a packet...
+ if (sample_counter == 0 ) begin
+ //check for overrun
+ if ( ph_full || ((CD_FIFO_SIZE -
cd_usedw) < SAMP_PER_PKT ) ) begin
+ pause = 1;
+ overrun = 1;
+ end
+ else begin
+ //good to go
+ pause = 0;
+
+ //save the temp header info
(timestamp, etc)
+ o_header = i_header_data;
+ end
+ end
+
+ //Sample on wren
+ if (!pause) begin
+ //debug: payload data
+ //temp_i = sample_counter;
+ //temp_q = i_header_data[`CB_TIMESTAMP];
+
+ temp_i = i_chan_data_i;
+ temp_q = i_chan_data_q;
+
+ wr_data = 1;
+ end
+
+ end // if wren
+
+ //ouput data to fifo and handling interleaving
+ //this is outside of wren condition for interleaving
+ if (wr_data) begin
+
+ if (interleaved) begin
+ if (sample_counter[0]) begin //Q on
odd samples
+ o_chan_data = temp_q;
+ wr_data = 0;
+ end
+ else
+ o_chan_data = temp_i;
+ //keep wr_data, still need q
+ end
+ else begin //not interleaved
+ o_chan_data = temp_i;
+ wr_data = 0;
+ end
+
+ sample_counter = sample_counter + 1;
+ cd_wren = 1;
+
+ end
+
+ //check for a forced flush (command channel used this)
+ if (flush_packet)
+ wr_header = 1;
+
+ //time to save the header?
+ //we don't need to wait for wren to push the header
+ if ( wr_header || (sample_counter == SAMP_PER_PKT ) )
begin
+ o_header[`CB_PAYLOAD_LEN] =
(sample_counter<<1); //actual payload length (x2 bytes)
+ o_header[`CB_OVERRUN] = overrun;
+ overrun = 0; //clear overrun once we have
saved the header
+ sample_counter = 0;
+ ph_wren = 1; //enable the ph fifo
+ wr_header = 0; //did it
+ end
+
+ end // else reset
+ end //always
+
+ //debug
+ assign dbg_sample_counter = sample_counter;
+
+endmodule
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_packetizer_b.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_packetizer_b.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_packetizer_b.v
2008-09-15 15:54:38 UTC (rev 9580)
@@ -0,0 +1,125 @@
+// rx_packetizer_b.v
+
+// NOTE: This is not currently functional
+
+// This version try to totally fill the fifo before signaling an overrun.
+
+// Sampling and overrun logic
+// Keep track of how many samples we have saved so we can save header
+// info at the right time.
+//
+// Overrun behavior is to fill the data fifo until full, at which
+// time sampling stops and the header is pushed with the current payload size
+// and the ovverrun bit set. Sampling is suspended until there is room for
+// a complete packet.
+// If the header fifo is full (unlikely, and which would happen after
+// completing a packet) sampling is suspended. The saved header is pushed
+// when there is room.
+// In any case, all samples in a packet should be contiguous.
+
+
+module rx_packetizer_b
+#(
+ parameter PH_FIFO_SIZE = 128, //Depth of header fifo
+ parameter PH_FIFO_SZ_L2 = 7, //log2(SIZE)
+ parameter CD_FIFO_SIZE = 1024, //Depth of channel data fifo
+ parameter CD_FIFO_SZ_L2 = 10
+)(
+ input reset,
+ input wrclk,
+ input interleaved,
+ input wren,
+ input flush_packet, //will
send non-full packet
+
+ input [63:0] i_header_data,
+ input [15:0] i_chan_data_i,
+ input [15:0] i_chan_data_q,
+
+ input [PH_FIFO_SZ_L2-1:0] ph_usedw,
+ input ph_full,
+
+ input [CD_FIFO_SZ_L2-1:0] cd_usedw,
+ input cd_full,
+
+ output reg ph_wren,
//packet header fifo enable
+ output reg cd_wren,
//channel data fifo enable
+ output reg overrun,
+
+ output reg [63:0] temp_header,
+ output reg [15:0] temp_data
+
+ //Debug
+ ,output [7:0] dbg_sample_counter
+);
+
+ parameter SAMP_PER_PKT = 252; //16 bit samples
+
+
+ reg [7:0] sample_counter;
+ reg save_header; //flag to set ph_wren when available
+
+ always @ ( posedge wrclk ) begin
+ if (reset) begin
+ sample_counter <= 8'd0;
+ overrun = 1'b0;
+ save_header = 1'b0;
+ ph_wren <= 1'b0;
+ cd_wren = 1'b1; //enable by default
+ end
+ else begin
+ //Check cd fifo for overrun
+ if (cd_full) begin
+ //only save header once
+ if (!overrun)
+ save_header = 1'b1;
+
+ overrun = 1'b1;
+ cd_wren = 1'b0;
+ end
+
+ if ( flush_packet || (sample_counter == SAMP_PER_PKT) )
+ save_header = 1'b1;
+
+ if (save_header) begin
+ //Header fifo full?
+ if (ph_full) begin
+ overrun = 1'b1;
+ cd_wren = 1'b0; //No more data if
ph_fifo is full
+ ph_wren <= 1'b0;
+ end
+ else begin
+ //Save the header
+ temp_header[`CB_PAYLOAD_LEN] =
(sample_counter<<1); //actual payload length (x2 bytes)
+ sample_counter <= 8'd0; //start
counting new packet
+ ph_wren <= 1'b1; //enable the fifo
+ save_header = 1'b0; //it has been
done
+ end
+ end
+ else
+ ph_wren <= 1'b0;
+
+
+ //Can we resume saving channel data?
+ if (!ph_full && (cd_usedw < (CD_FIFO_SIZE -
SAMP_PER_PKT)))
+ cd_wren = 1'b1;
+
+
+ //If we are saving chan data...
+ if (wren && cd_wren) begin
+ //if this is first sample, save the temp header
info (timestamp, etc)
+ if (!sample_counter) begin
+ temp_header = i_header_data;
+ temp_header[`CB_OVERRUN] = overrun;
+ overrun = 1'b0; //only clear overrun
once we have sent the packet
+ end
+ sample_counter <= sample_counter + 8'd1;
+ end
+
+ end //else
+ end //always
+
+
+ //debug
+ assign dbg_sample_counter = sample_counter;
+
+endmodule
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
2008-09-15 15:48:31 UTC (rev 9579)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.qsf
2008-09-15 15:54:38 UTC (rev 9580)
@@ -46,4 +46,6 @@
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to |
-section_id Top
\ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to |
-section_id Top
+set_global_assignment -name VERILOG_FILE ../rx_packetizer_b.v
+set_global_assignment -name VERILOG_FILE ../rx_packetizer_a.v
\ No newline at end of file
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
2008-09-15 15:48:31 UTC (rev 9579)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/rx_buffer_inband_tb.v
2008-09-15 15:54:38 UTC (rev 9580)
@@ -83,6 +83,17 @@
);
+//parameter CHAN_END_AT = 32'h000003f0;
+parameter CHAN_END_AT = 32'hffffffff;
+
+parameter FX2_BEGIN_AT = 32'h00000000;
+//parameter FX2_BEGIN_AT = 32'h00001500
+
+parameter FX2_PKT_READS = 9'd257;
+
+
+ wire [63:0] dbg_mux_header_data;
+
//Channel inputs
wire [3:0] num_chan;
assign num_chan = 4'd2;
@@ -204,7 +215,7 @@
/////////////////////////////////////////////
// Strobe input
- assign rxstrobe = !reset & timestamp[2] && !timestamp[1:0];
+ assign rxstrobe = timestamp < CHAN_END_AT ? !reset & timestamp[2] &&
!timestamp[1:0] : 1'b0;
/////////////////////////////////////////////
//generate sawtooth channel input from timestamp
@@ -266,11 +277,6 @@
/////////////////////////////////////////////
//control FX2 reads
-`define FX2_PKT_READS 9'd257
-
-`define FX2_BEGIN_AT 32'h00000000
-//`define FX2_BEGIN_AT 32'h00000806
-
assign usb_reset = reset;
always @ (negedge usbclk)
@@ -279,9 +285,9 @@
usb_rd <= 1'd0;
end
else begin
- if (!usb_rd && usb_pkt_rdy && (timestamp >=
`FX2_BEGIN_AT ) )
+ if (!usb_rd && usb_pkt_rdy && (timestamp >=
FX2_BEGIN_AT ) )
usb_rd <= 1'd1;
- else if (usb_counter >= (`FX2_PKT_READS - 1))
+ else if (usb_counter >= (FX2_PKT_READS - 1))
usb_rd <= 1'd0;
end
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2008-09-15 15:48:31 UTC (rev 9579)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2008-09-15 15:54:38 UTC (rev 9580)
@@ -232,9 +232,9 @@
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name INC_PLC_MODE OFF
@@ -326,7 +326,6 @@
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id SCLK
# end CLOCK(SCLK)
# ---------------
@@ -338,7 +337,6 @@
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id master_clk
# end CLOCK(master_clk)
# ---------------------
@@ -350,7 +348,6 @@
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
-set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS
OFF -section_id usbclk
# end CLOCK(usbclk)
# -----------------
@@ -376,9 +373,14 @@
set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD OFF
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 20
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 400
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 20
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz"
+set_global_assignment -name VERILOG_FILE ../../inband_lib/inband_packet_defs.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_packetizer_a.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_channel_selector.v
set_global_assignment -name VERILOG_FILE ../../megacells/dcfifo_generic.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/inband_packet_defs.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_channel_buffer.v
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4kx16_dc.v
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1kx16.v
@@ -427,4 +429,6 @@
set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_builder.v
\ No newline at end of file
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
\ No newline at end of file
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- [Commit-gnuradio] r9580 - in gnuradio/branches/developers/ets/inband/usrp/fpga: inband_lib inband_lib/tb toplevel/usrp_inband_usb,
ets <=