[Commit-gnuradio] [gnuradio] 119/148: better debug pins

[git]

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nwest pushed a commit to annotated tag old_usrp_devel_udp
in repository gnuradio.

commit b39fb27693c287e24437452a0a77d7c738ae454b
Author: Matt Ettus <address@hidden>
Date:   Tue Jan 5 22:29:09 2010 -0800

    better debug pins
---
 usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v |  7 +++----
 usrp2/fpga/top/u2_core/u2_core.v                 | 11 ++++++-----
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v 
b/usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v
index 11cf7ee..10089f1 100644
--- a/usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v
+++ b/usrp2/fpga/simple_gemac/simple_gemac_wrapper19.v
@@ -148,18 +148,17 @@ module simple_gemac_wrapper19
    
    wire [31:0]           debug_tx, debug_rx;
 
-   /*
    assign debug_tx  = { { tx_ll_data },
                        { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
                          tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, 
tx_ll_dst_rdy2 },
-                       { tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, 
tx_f19_dst_rdy_int1, tx_f19_data_int1[34:32]},
+                       { tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, 
tx_f19_dst_rdy_int1, tx_f19_data_int1[18:16]},
                        { tx_data} };
    assign debug_rx  = { { rx_ll_data },
                        { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
                          rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, 
rx_ll_dst_rdy2 },
-                       { rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, 
rx_f19_dst_rdy_int1, rx_f19_data_int1[34:32]},
+                       { rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, 
rx_f19_dst_rdy_int1, rx_f19_data_int1[18:16]},
                        { rx_data} };
-    */
+
    assign debug  = debug_rx;
    
 endmodule // simple_gemac_wrapper19
diff --git a/usrp2/fpga/top/u2_core/u2_core.v b/usrp2/fpga/top/u2_core/u2_core.v
index 11159ee..26ad2d1 100644
--- a/usrp2/fpga/top/u2_core/u2_core.v
+++ b/usrp2/fpga/top/u2_core/u2_core.v
@@ -158,8 +158,8 @@ module u2_core
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         atr_lines;
 
-   wire [31:0]         debug_rx, debug_mac, debug_mac0, debug_mac1, 
debug_tx_dsp, debug_txc, 
-               debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
+   wire [31:0]         debug_rx, debug_mac, debug_mac0, debug_mac1, 
debug_tx_dsp, debug_txc,
+               debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, 
debug_udp;
 
    wire [15:0]         ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, 
eth_rx_occ, eth_tx_occ, eth_rx_occ2;
    wire        ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, 
eth_rx_full, eth_tx_full, eth_rx_full2;
@@ -445,7 +445,8 @@ module u2_core
       .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), 
.rx_f19_dst_rdy_o(rx_f19_dst_rdy),
       .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), 
.tx_f19_dst_rdy_i(tx_f19_dst_rdy),
       .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy_o(wr2_ready_i), 
.rx_f36_dst_rdy_i(wr2_ready_o),
-      .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy_i(rd2_ready_o), 
.tx_f36_dst_rdy_o(rd2_ready_i) );
+      .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy_i(rd2_ready_o), 
.tx_f36_dst_rdy_o(rd2_ready_i),
+      .debug(debug_udp) );
    
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #7
@@ -742,8 +743,8 @@ module u2_core
                             { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, 
rd2_ready_i, rd2_ready_o } };
  */
 
-   assign debug = debug_vt;
-   assign debug_gpio_0 = sample_tx;
+   assign debug = debug_udp;
+   assign debug_gpio_0 = debug_mac;
    assign debug_gpio_1 = 32'hDEAD_BEEF;
    
 endmodule // u2_core