I knew that integrating the Viterbi algorithm on the receiver side is going to take a lot of work. And I had seen gr-trellis folder, which had the Viterbi decoder implementation, which I was planning to use for the time being.
I was thinking of atleast integrating the encoder on the transmitting side first.
I think that if I replicate the transmitter side steps (steps 2 to 5 in my earlier post) in Verilog on the FPGA, then the data packets getting transmitted from transmitter side would be same as the current implementation. Then, I can use the existing Achilleas's Viterbi decoder on the receiver side to decode my data for the time being. *~* Any comments ? *~*
I am not sure, but dont see a reason why this should'nt work !
Does anyone has any comments on *~*~* if 4 steps (in Verilog) in my earlier post, would 'replicate' the existing transmitting steps or anything else needs to be added? *~*~*
I plan to finish the transmitter side implementation as soon as possible and then moving ahead.