Re: [Discuss-gnuradio] Question about uO and FPGA

[DiX]

George Nychis wrote:
> 
> 
> 
> DiX wrote:
>>     The problem is I have to use relatively high bit rate on these tx and
>> rx
>> paths. The demic rate should be <=16, and interp rate <=32. When I run
>> the
>> code with decim rate = 16 interp rate = 32, I keep receiving uO. My
>> questions are : what's the max rate the USRP can support in this case?
>> and
>> is there any fatal fault in my graph design?
> 
> Hi Di,
> 
> uO means that the USRP is overrunning, in other words your host machine 
> cannot keep up with the incoming data rate.
> 
> The USRP cannot keep up with more than 8Msps due to the USB bus 
> limitation with 32-bit complex.  You will get overruns if you try 
> anything more than this.  Let's take the case of a single 
> daughterboard... you will not be able to use a decimation rate lower 
> than 8 (64Msps/8 = 8Msps).
> 
> The first thing to do, is to check to see if your machine can keep up 
> with 8Msps.  Run "./usrp/host/apps/test_usrp_standard_rx -D 8" and see 
> if you get any uO.  If not, keep increasing the decimation until you get 
> no uO.
> 
> Since you're using two RX chains, with a decimation rate of 8, you'd be 
> generating 16Msps since each chain generates 8Msps.  Therefore, when you 
> say "decim rate should be <=16" ... <=16 is not possible, only =16. 
> With decim=16 you're generating 4Msps per chain, for a total of 8Msps.
> 
> - George
> 
> 


Hi George,

     Thanks for your prompt reply :-)

     I understand the USB2.0 can be a bottleneck. So I try to connect the
data from one d'b to the other d'b directly in a graph without making the
data travel through USB (I do not need to module/demodule the signal).
Actually if I have only one rx path on say A, and one tx path on B, it
relays from A to B quite well with decim=16 and interp=32. However when I
try to use 2 rx and 2 tx in the way I discribed in last post, it fails and
prints many uO. 

     Is it possible the total data rate is too high to be supported in the
FPGA? Sorry I know little about FPGA. 

     -Di










 
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