RE: [Discuss-gnuradio] USRP1, FPGA and ADC clock

[Przemyslaw Dmochowski]

Hi,
I use one of my USRP's for other things than radio (ultrasound imaging) and I 
my idea was it would be beneficial to run the FPGA at a higher frequency than 
the ADC (n*ADC_CLK). I was writing my own FPGA code for that and since CLKOUT1 
and CLKOUT2 are not wired to FPGA, I just have no idea how to synchronize the 
ADC data with the clock.

The reason for separating the ADC clock from the FPGA clock is that the ADC 
clock is not clean enough for my experiments.

I also discovered that if I remove R1012 from "master_clock" and connect it to 
any other output of AD9513 the USRP runs unstable. I get random "ADC code 
jumps" when reading the data from ADC and that depends on the length of the 
wire connecting the R1012 to the clock,  which looks like the ADC data is read 
by FPGA somewhere on the edge.

I didn't investigate the original FPGA code but If really there is no 
synchronization clock between the FPGA and ADC apart from the master_clock then 
it means that it is only a coincidence that the USRP works at all.

In this case whether the data is read correctly depends on the clock track 
length from AD9513 to AD9862 and AD9513 to FPGA. Since it is difficult to 
estimate the delays in the ADC one doesn't really know in which moment the ADC 
outputs the data in respect to the clock.

Is it true that the phase of the master_clock at FPGA and ADC is important to 
get correct readings?

Sorry for a long email but I just try to understand the hardware and whether I 
will be able to get my FPGA code to get working.

Przemek


-----Original Message-----
From: Matt Ettus [mailto:address@hidden 
Sent: 11 February 2011 19:13
To: Przemyslaw Dmochowski
Cc: address@hidden
Subject: Re: [Discuss-gnuradio] USRP1, FPGA and ADC clock


The FPGA and ADC are run off of the same clock, directly from the main 
oscillator.  They need to be the same frequency.  Why would you want to 
use different clocks?

Matt


On 02/10/2011 05:15 AM, Przemyslaw Dmochowski wrote:
> Hi,
>
> I was wonder how the RX and TX data from/to ADC is read by Altera FPGA.
>
> I see from the schematics that FPGA and ADC take the clock from the same
>
> output of AD9513.
>
>  From Ad9862 I read that the ADC data is latched using CLKOUT1, but this
> output is not connected
>
> to FPGA, so at which moment is the data from ADC sampled by FPGA, with
> which clock?
>
> And the same question about latching the DAC data in AD9862 send from FPGA.
>
> I looked at the clock and it looks distorted and I wanted
>
> to separate the ADC and FPGA clocks.
>
> Is it possible to drive the FPGA and ADC from different clock sources? Are
>
> different frequencies for FPGA and ADC allowed?
>
> Do the clocks have to be synchronized? If not how much phase shift between
>
> ADC clock and FPGA clock is allowed?
>
> Thanks,
>
> Przemek
>
>
>
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