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Re: [Help-gnucap] verilog-ams instance loading
From: |
al davis |
Subject: |
Re: [Help-gnucap] verilog-ams instance loading |
Date: |
Mon, 26 Jan 2009 22:15:27 -0500 |
User-agent: |
KMail/1.9.9 |
Look here:
http://wiki.gnucap.org/dokuwiki/doku.php?id=gnucap:languages:verilog
On Monday 26 January 2009, John Griessen wrote:
> module verilog_io ( GND , OUT , IN );
> capacitor #(.c(1250e-9) ) C1 ( .p(B), .n(GND));
> inductor #(.l(.001) ) L1 ( .n(OUT), .p(B));
> resistor #(.r(1000) ) R1 ( .n(B), .p(IN));
> endmodule
> verilog_io1 verilog_io ( .GND(0) , OUT(VOUT), .IN(VIN));
You are trying to create an instance of "verilog_io1" with a
name "verilog_io".
and it says:
> gnucap-verilog>include ./verilog_io.net
> verilog_io1 verilog_io ( .GND(0) , OUT(VOUT), .IN(VIN));
> ^ ? verilog_io1: no match
because it doesn't recognize "verilog_io1".
Try switching around the names:
verilog_io verilog_io1 ( .GND(0) , OUT(VOUT), .IN(VIN));