Deriving dependency from target

[Eitan Rabin]

Hi,

 

1)

 

I'm try to build the following rule:

 

TARGET = myexe

 

myexe_SOURCES = foo.c bob.c bar.c

 

$(TARGET): $($(@:%=%_SOURCES))

    gcc ...

 

This doesn't work.

 

Is there a similar way to create such makefile without having to create temporary makefiles.

 

2) I was curious to know what is the reason that variable in dependencies are replaced immediatly. This requires to make all variable definition before the rules which is not clean in many cases. Anyone know the reason for that?

 

Thanks.