Re: multiple targets for a single command

[Paul D. Smith]

%% Jonathan Baccash <address@hidden> writes:

  jb> Ok, in my attempt to dumb down the example, I guess I dumbed it down a
  jb> bit too much.... In reality, the command I'm running is lib.exe, which
  jb> comes with the visual studio compiler.  When I run lib /DEF:my.def,
  jb> the outputs created are my.exp and my.lib.  Some commands depend on
  jb> my.exp, and others on my.lib.

  jb> So the actual makefile would be more like
  jb> my.dll: my.exp my.obj
  jb>       link /DLL $^

  jb> my.exp: my.lib

  jb> my.lib: my.def
  jb>       lib /DEF:my.def

You should consider writing this with pattern rules, like:

    my.dll: my.exp my.obj
            ...

    %.exp %.lib : %.def
            ...

That will do what you want.

  jb> I don't think I'm really hiding anything from make here.  I told
  jb> make that to update my.exp, it needs to update my.lib.  Ok, it did
  jb> that, and then it thought my.exp was not newer than my.dll.

Make knows that it didn't run any rules, so it "knows" that my.exp could
not have been updated.  In fact, the "my.exp: my.lib" statement is not a
full rule: it's just a prerequisite declaration.

If you want make to re-check whether my.exp was actually updated you
have to give it a rule, even if it's empty:

     my.exp: my.lib
            @:

or whatever.

-- 
-------------------------------------------------------------------------------
 Paul D. Smith <address@hidden>          Find some GNU make tips at:
 http://www.gnu.org                      http://make.paulandlesley.org
 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist