Re: Makefile C vs C++

[Hernán]

Thank you very much Greg,
I've taken a look at that folder, and there is one Makefile, and several
files with the format *.makefile.
What I did, initially was to look for the word gcc, but as it seems it
didn't work (*). After I saw in the main Makefile some sections that seems
to invoque the compilator, but I don't know how to know what macro is.

As it is shown in next paragraphs, that sections includes the calls to
ADD_RULE_TEMPLATE and GENERIC_RULES_TEMPLATE. I think they both set the
compiler with the macro $(1), but, how is that determined?, I suppose that
is the first argument given to the function, but in the call sentence it
doesn't seem to send the compiler type... at least is not in the format
"gcc" that I expected...

The section concerning ADD_RULE_TEMPLATE is the following :

> define ADD_RULE_TEMPLATE
>   ifeq ($$(USE_$(shell echo $(1) | tr "a-z" "A-Z")),yes)
>     TO_BUILD+=build_$(1)
>   endif
> endef
>
> # Add rule for each target
> $(foreach target,$(TARGETS),$(eval $(call ADD_RULE_TEMPLATE,$(target))))
>

After, the section concerning GENERIC_RULE_TEMPLATE is :

> .PHONY: $(foreach target,$(TARGETS),build_$(target) clean_$(target))
>
> all $(MAKECMDGOALS): $(TO_BUILD)
>     @if [ $(MAKECMDGOALS) ] && [ $(MAKECMDGOALS) = check ] ; then
> $(SDK_SOURCE_DIR)/Build/cvsstatus.sh $(SDK_SOURCE_DIR)/Build END ; fi
>
> before_check:
>     @if [ $(MAKECMDGOALS) ] && [ $(MAKECMDGOALS) = check ] ; then rm -rf
> *.log ; fi
>
> define GENERIC_RULES_TEMPLATE
>   ifneq ($(1),dll)
>     build_$(1): before_check
>     @$(MAKE) -f $(1).makefile $(MAKECMDGOALS)
>   endif
> endef
>
> build_dll: before_check
>     @$(MAKE) -f app.makefile $(MAKECMDGOALS)
>
>
> # Build rules for each target
> $(foreach target,$(TARGETS),$(eval $(call
> GENERIC_RULES_TEMPLATE,$(target))))
>

(*)
I saw that in the main Makefile, there are some calls to two of those files
*.makefile, which seems to check the variables and versions. The others
*.makefile dont seem to be used, but in one of them I found a
common.makefile which defines a macro called XCC,
(XCC=$(GENERIC_COMMAND_PREFIX)gcc). Again, some macros are not defined in
the makefile. This GENERIC_COMMAND_PREFIX is defined in some other
sysvar.makefile, which is usually called in the main Makefile to throw
errors and say the version of gcc. Which I think could omit. I'm mentioning
that just in case I omit something important.

If necessary I could send more information. I hope the explanation was
clear.

Thank you again for your time,

Hernán


2012/9/18 Greg Chicares <address@hidden>

> On 2012-09-17 19:25Z, Hernán F.B. wrote:
> > I'm trying to include in an ANSI C project, some (OpenCV) libraries made
> in
> > c++.
> > Basically people told me to change the compiler to the g++, but the
> > makefile of this project is quite unusual for my experience in makefiles,
> > and I don't find out what macro to change. It uses some standard make
> > variables like MAKECMDGOALS and MAKE (which calls recursively makefile).
> > Here is the main part of the make file (without the macro's declaration):
> >
> > .PHONY: $(TARGET) build_libs
> >
> > all: build_libs $(TARGET)
> >
> > $(TARGET):
> >     @$(MAKE) -C $(SDK_PATH)/VP_SDK/Build $(TMP_SDK_FLAGS) $(SDK_FLAGS)
> $(MAKECMDGOALS) USE_LINUX=yes
>
> As you said, this invokes 'make' recursively. The '-C' option
> invokes 'make' in directory $(SDK_PATH)/VP_SDK/Build . Probably
> that directory contains a submakefile that invokes the compiler.
> Examine that submakefile to determine what changes may be needed
> to support C++.
>
>
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