[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [PATCH 3/5] ast2400: pretend DMAs are done for U-boot
From: |
Cédric Le Goater |
Subject: |
[Qemu-arm] [PATCH 3/5] ast2400: pretend DMAs are done for U-boot |
Date: |
Fri, 8 Jul 2016 18:06:54 +0200 |
U-boot does SPI timing calibration using DMA tranfers. To let the
initialization continue, we fake success by setting the DMA status of
the Interrupt Control Register.
For the moment, DMA support is not required as it is not used in
normal operation.
Signed-off-by: Cédric Le Goater <address@hidden>
---
hw/ssi/aspeed_smc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 854474b642ea..d319e04a27f0 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -273,6 +273,9 @@ static void aspeed_smc_reset(DeviceState *d)
memset(s->regs, 0, sizeof s->regs);
+ /* Pretend DMA is done (u-boot initialization) */
+ s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS;
+
/* Unselect all slaves */
for (i = 0; i < s->num_cs; ++i) {
s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
@@ -297,6 +300,7 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr,
unsigned int size)
if (addr == s->r_conf ||
addr == s->r_timings ||
addr == s->r_ce_ctrl ||
+ addr == R_INTR_CTRL ||
(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)) {
return s->regs[addr];
} else {
--
2.1.4
- [Qemu-arm] [PATCH 0/5] ast2400: some cleanups and a simple memory controller model, Cédric Le Goater, 2016/07/08
- [Qemu-arm] [PATCH 1/5] hw/misc: fix typo in Aspeed SCU hw-strap2 property name, Cédric Le Goater, 2016/07/08
- [Qemu-arm] [PATCH 2/5] ast2400: replace aspeed_smc_is_implemented(), Cédric Le Goater, 2016/07/08
- [Qemu-arm] [PATCH 3/5] ast2400: pretend DMAs are done for U-boot,
Cédric Le Goater <=
- [Qemu-arm] [PATCH 4/5] ast2400: externalize revision numbers, Cédric Le Goater, 2016/07/08
- [Qemu-arm] [PATCH 5/5] ast2400: add a memory controller device model, Cédric Le Goater, 2016/07/08
- Re: [Qemu-arm] [PATCH 0/5] ast2400: some cleanups and a simple memory controller model, Peter Maydell, 2016/07/12