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[Qemu-arm] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX
From: |
Alex Bennée |
Subject: |
[Qemu-arm] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX |
Date: |
Fri, 13 Oct 2017 17:24:25 +0100 |
Signed-off-by: Alex Bennée <address@hidden>
---
target/arm/helper-a64.c | 18 ++++++++++++++++++
target/arm/helper-a64.h | 1 +
target/arm/translate-a64.c | 45 +++++++++++++++++++++++++++++++++++----------
3 files changed, 54 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 8ef15c4c45..dd26675d5c 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -559,3 +559,21 @@ ADVSIMD_HALFOP(min)
ADVSIMD_HALFOP(max)
ADVSIMD_HALFOP(minnum)
ADVSIMD_HALFOP(maxnum)
+
+/* Data processing - scalar floating-point and advanced SIMD */
+
+float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+
+ a = float16_squash_input_denormal(a, fpst);
+ b = float16_squash_input_denormal(b, fpst);
+
+ if ((float16_is_zero(a) && float16_is_infinity(b)) ||
+ (float16_is_infinity(a) && float16_is_zero(b))) {
+ /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
+ return make_float16((1U << 14) |
+ ((float16_val(a) ^ float16_val(b)) & (1U << 15)));
+ }
+ return float16_mul(a, b, fpst);
+}
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index a4ce87970e..0f97eb607f 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -52,3 +52,4 @@ DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f687bab214..d12106695f 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10648,7 +10648,7 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
}
/* fall through */
case 0x9: /* FMUL, FMULX */
- if (!extract32(size, 1, 1)) {
+ if (!extract32(size, 1, 1) && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
{
unallocated_encoding(s);
return;
}
@@ -10660,18 +10660,30 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
}
if (is_fp) {
- /* low bit of size indicates single/double */
- size = extract32(size, 0, 1) ? 3 : 2;
- if (size == 2) {
+ /* convert insn encoded size to TCGMemOp size */
+ switch (size) {
+ case 0: /* half-precision */
+ size = MO_16;
+ index = h << 2 | l << 1 | m;
+ break;
+ case 2: /* single precision */
+ size = MO_32;
index = h << 1 | l;
- } else {
+ rm |= (m << 4);
+ break;
+ case 3: /* double precision */
+ size = MO_64;
if (l || !is_q) {
unallocated_encoding(s);
return;
}
index = h;
+ rm |= (m << 4);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
}
- rm |= (m << 4);
} else {
switch (size) {
case 1:
@@ -10805,10 +10817,23 @@ static void disas_simd_indexed(DisasContext *s,
uint32_t insn)
gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res,
fpst);
break;
case 0x9: /* FMUL, FMULX */
- if (u) {
- gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
- } else {
- gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
+ switch (size) {
+ case 1:
+ if (u) {
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx,
fpst);
+ } else {
+ g_assert_not_reached();
+ }
+ break;
+ case 2:
+ if (u) {
+ gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
+ } else {
+ gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
+ }
+ break;
+ default:
+ g_assert_not_reached();
}
break;
case 0xc: /* SQDMULH */
--
2.14.1
- [Qemu-arm] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns, (continued)
- [Qemu-arm] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns, Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN, Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix, Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX, Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV), Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX,
Alex Bennée <=
- [Qemu-arm] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support, Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation, Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same, Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework, Alex Bennée, 2017/10/13
- [Qemu-arm] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode, Alex Bennée, 2017/10/13