[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled
From: |
Richard Henderson |
Subject: |
[PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled |
Date: |
Sat, 1 Oct 2022 09:22:55 -0700 |
Do not apply memattr or shareability for Stage2 translations.
Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the
pseudocode in AArch64.S1DisabledOutput.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Do not use a switch or a goto.
---
target/arm/ptw.c | 48 +++++++++++++++++++++++++-----------------------
1 file changed, 25 insertions(+), 23 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index e494a9de67..8d27a98a42 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2282,11 +2282,12 @@ static bool get_phys_addr_disabled(CPUARMState *env,
target_ulong address,
GetPhysAddrResult *result,
ARMMMUFaultInfo *fi)
{
- uint64_t hcr;
- uint8_t memattr;
+ uint8_t memattr = 0x00; /* Device nGnRnE */
+ uint8_t shareability = 0; /* non-sharable */
if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
int r_el = regime_el(env, mmu_idx);
+
if (arm_el_is_aa64(env, r_el)) {
int pamax = arm_pamax(env_archcpu(env));
uint64_t tcr = env->cp15.tcr_el[r_el];
@@ -2314,32 +2315,33 @@ static bool get_phys_addr_disabled(CPUARMState *env,
target_ulong address,
*/
address = extract64(address, 0, 52);
}
+
+ /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
+ if (r_el == 1) {
+ uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure);
+ if (hcr & HCR_DC) {
+ if (hcr & HCR_DCT) {
+ memattr = 0xf0; /* Tagged, Normal, WB, RWA */
+ } else {
+ memattr = 0xff; /* Normal, WB, RWA */
+ }
+ }
+ }
+ if (memattr == 0 && access_type == MMU_INST_FETCH) {
+ if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
+ memattr = 0xee; /* Normal, WT, RA, NT */
+ } else {
+ memattr = 0x44; /* Normal, NC, No */
+ }
+ shareability = 2; /* outer sharable */
+ }
+ result->cacheattrs.is_s2_format = false;
}
result->phys = address;
result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
result->page_size = TARGET_PAGE_SIZE;
-
- /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
- hcr = arm_hcr_el2_eff_secstate(env, is_secure);
- result->cacheattrs.shareability = 0;
- result->cacheattrs.is_s2_format = false;
- if (hcr & HCR_DC) {
- if (hcr & HCR_DCT) {
- memattr = 0xf0; /* Tagged, Normal, WB, RWA */
- } else {
- memattr = 0xff; /* Normal, WB, RWA */
- }
- } else if (access_type == MMU_INST_FETCH) {
- if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
- memattr = 0xee; /* Normal, WT, RA, NT */
- } else {
- memattr = 0x44; /* Normal, NC, No */
- }
- result->cacheattrs.shareability = 2; /* outer sharable */
- } else {
- memattr = 0x00; /* Device, nGnRnE */
- }
+ result->cacheattrs.shareability = shareability;
result->cacheattrs.attrs = memattr;
return 0;
}
--
2.34.1
- [PATCH v3 13/42] target/arm: Introduce arm_hcr_el2_eff_secstate, (continued)
- [PATCH v3 13/42] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/10/01
- [PATCH v3 10/42] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/10/01
- [PATCH v3 11/42] target/arm: Reorg regime_translation_disabled, Richard Henderson, 2022/10/01
- [PATCH v3 15/42] target/arm: Remove env argument from combined_attrs_fwb, Richard Henderson, 2022/10/01
- [PATCH v3 12/42] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/10/01
- [PATCH v3 14/42] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/10/01
- [PATCH v3 16/42] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/10/01
- [PATCH v3 07/42] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/10/01
- [PATCH v3 08/42] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/10/01
- [PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled,
Richard Henderson <=
- [PATCH v3 20/42] target/arm: Use tlb_set_page_full, Richard Henderson, 2022/10/01
- [PATCH v3 22/42] target/arm: Use probe_access_full for MTE, Richard Henderson, 2022/10/01
- [PATCH v3 09/42] target/arm: Add is_secure parameter to do_ats_write, Richard Henderson, 2022/10/01
- [PATCH v3 17/42] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/10/01
- [PATCH v3 18/42] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/10/01
- [PATCH v3 23/42] target/arm: Use probe_access_full for BTI, Richard Henderson, 2022/10/01