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Re: [PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled


From: Peter Maydell
Subject: Re: [PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled
Date: Thu, 6 Oct 2022 15:33:27 +0100

On Sat, 1 Oct 2022 at 17:53, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Do not apply memattr or shareability for Stage2 translations.
> Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the
> pseudocode in AArch64.S1DisabledOutput.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v3: Do not use a switch or a goto.
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM



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