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[Qemu-commits] [qemu/qemu] 34f560: target-mips: Fix incorrect code and t
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[Qemu-commits] [qemu/qemu] 34f560: target-mips: Fix incorrect code and test for INSV |
Date: |
Thu, 06 Dec 2012 00:30:10 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 34f5606ee101f82a247d09d05644ad2a63c8e342
https://github.com/qemu/qemu/commit/34f5606ee101f82a247d09d05644ad2a63c8e342
Author: Petar Jovanovic <address@hidden>
Date: 2012-12-05 (Wed, 05 Dec 2012)
Changed paths:
M target-mips/dsp_helper.c
M tests/tcg/mips/mips32-dsp/insv.c
Log Message:
-----------
target-mips: Fix incorrect code and test for INSV
Content of register rs should be shifted for pos before applying a mask.
This change contains both fix for the instruction and to the existing test.
Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Commit: 19e6c50d2d843220efbdd3b2db21d83c122c364a
https://github.com/qemu/qemu/commit/19e6c50d2d843220efbdd3b2db21d83c122c364a
Author: Petar Jovanovic <address@hidden>
Date: 2012-12-05 (Wed, 05 Dec 2012)
Changed paths:
M target-mips/dsp_helper.c
M tests/tcg/mips/mips32-dsp/shilo.c
M tests/tcg/mips/mips32-dsp/shilov.c
Log Message:
-----------
target-mips: Fix incorrect shift for SHILO and SHILOV
helper_shilo has not been shifting an accumulator value correctly for negative
values in 'shift' field. Minor optimization for shift=0 case.
This change also adds tests that will trigger issue and check for regressions.
Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Compare: https://github.com/qemu/qemu/compare/80625b97b528...19e6c50d2d84
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