Re: SV: [Qemu-devel] ARM CPSR and conditional instructions

[Wolfgang Schildbach]

I very much doubt there is any problem with the CPSR. The ARM emulation 
has correctly run hundreds of millions of instructions coming from many 
different compilers and hand-written assembly. Can you be more precise in 
what the effect is that you see?

- Wolfgang

address@hidden 
wrote on 22.11.2006 22:13:01:

> I?m sorry for spamming you mailing list with my duplicate posts. I 
> had some problems sending my mail. 
> 
> /Torbjörn
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> [mailto:address@hidden För 
> Torbjörn Andersson
> Skickat: den 21 november 2006 22:16
> Till: address@hidden
> Ämne: [Qemu-devel] ARM CPSR and conditional instructions
> 
> Hello qemu developers!
> 
> I´m using QEMU for some ARM debugging and I have som questions 
> regardning the CPSR register. I get the feeling that the CPSR 
> condition code bits, representing the results from the ALU, are not 
> maintained at all points. Is the JIT in QEMU tailored in any way 
> towards GCC output? (Resulting in issues with the output of other 
> compilers that make use of the conditional execution of instructions 
etc.)
> 
> What I want to do is to try to verify QEMU maintains the CPSR 
> register and if not fix it. However, it is not trivial identify 
> where the updates should be placed. The relationship between 
> translate.c and op.c is not trival I must say :)
> I would be happy I anyone here could give me some pointers on how 
> the updates of the CPSR register is done today and what the strategy
> is. I guess there are plenty of performance ideas here as in the rest of 
qemu.
> 
> Does anyone have any reflection on this topic or can anyone give me 
> some pointers?
> 
> Torbjörn
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