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Re: [Qemu-devel] [RFC] IRQ acknowledge on MIPS
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [RFC] IRQ acknowledge on MIPS |
Date: |
Tue, 23 Jan 2007 17:36:05 +0100 |
User-agent: |
IceDove 1.5.0.9 (X11/20061220) |
Alexander Voropay a écrit :
> "Aurelien Jarno" <address@hidden> wrote:
>
>> Then after playing with the current code, I am sure we are missing a
>> simple interrupt controller for the MIPS CPU. It supports 6 hardware
>> interrupts (IP2 to IP7) and we are using two of them in the current
>> emulation: one for the i8259a and the other for the timer. In both case
>> the current code assert and deassert a CPU_INTERRUPT_HARD.
>
> The Galileo GT64xxx chip contains an interrupt controller too (for DMA
> cycle indication, built-in Timers e.t.c.). All this interrupt controllers are
> daisy-chained: i8259(as part of the PIIX + PCI), GT64xxx and MIPS internal.
>
Yes, but this controller is not used on the Malta board.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' address@hidden | address@hidden
`- people.debian.org/~aurel32 | www.aurel32.net