Re: [Qemu-devel] [patch] make qemu work with GCC 4

[Michael Matz]

Hi,

On Thu, 30 Aug 2007, Thiemo Seufer wrote:

> > * ppc: adds -fno-section-anchors to OP_CFLAGS, as dyngen isn't prepared
> >        to deal with the relocs resulting from using section anchors
> 
> Maybe this should be handled more generally then, not ppc specific, like
> other "offending" compiler options: check if the compiler knows the
> option, if yes, disable the feature.

Yeah, like is done for the other additions to OP_CFLAGS, which are guarded 
by $(call cc-option, ...).

> >        I solved that by placing one of the T[012] operands into memory
> >        for HOST_I386, thereby freeing one reg.  Here's some justification 
> >        of why that doesn't really cost performance: with three free regs
> >        GCC is already spilling like mad in the snippets, we just trade one
> >        of those memory accesses (to stack) with one other mem access to 
> >        the cpu_state structure, which will be in cache.
> 
> Could you back up this assumption with some numbers? :-)

I did that downthread.  To me the slowdown is not significant enough, 
although it exists.

> > --- qemu-0.9.0.cvs.orig/target-arm/cpu.h    2007-06-24 14:09:48.000000000 
> > +0200
> > +++ qemu-0.9.0.cvs/target-arm/cpu.h 2007-08-21 21:38:36.000000000 +0200
> > @@ -52,6 +52,9 @@ typedef uint32_t ARMReadCPFunc(void *opa
> >   */
> >  
> >  typedef struct CPUARMState {
> > +#if defined(HOST_I386)
> > +    uint32_t t1;
> > +#endif
> >      /* Regs for current mode.  */
> >      uint32_t regs[16];
> >      /* Frequently accessed CPSR bits are stored separately for efficiently.
> > diff -urp qemu-0.9.0.cvs.orig/target-arm/exec.h 
> > qemu-0.9.0.cvs/target-arm/exec.h
> > --- qemu-0.9.0.cvs.orig/target-arm/exec.h   2007-06-03 19:44:36.000000000 
> > +0200
> > +++ qemu-0.9.0.cvs/target-arm/exec.h        2007-08-21 21:48:48.000000000 
> > +0200
> > @@ -23,7 +23,12 @@
> >  register struct CPUARMState *env asm(AREG0);
> >  register uint32_t T0 asm(AREG1);
> >  register uint32_t T1 asm(AREG2);
> > +#ifndef HOST_I386
> >  register uint32_t T2 asm(AREG3);
> > +#else
> > +#define T2 (env->t1)
> > +#endif
> 
> T2/t1 mismatch, it seems. Likewise for mips and ppc.

Yes, well, I could have named the env member perhaps "temp" :-)  I can 
change it, though.


Ciao,
Michael.