Re: [Qemu-devel] target_mmap and host vs target page sizes.

[Edgar E. Iglesias]

On Sun, Sep 30, 2007 at 06:45:08PM +0300, Blue Swirl wrote:
> On 9/30/07, Edgar E. Iglesias <address@hidden> wrote:
> > With this updated patch, I can now reliably run statically linked sparc64 
> > programs on my 32 bit host. Dynamically linked sparc64 programs reliably 
> > fail with an unhandled trap 0x37. qemu m68k reliably segfaults with and 
> > without the patch. Again, I tested CRIS and MIPS 8K and they both reliably 
> > manage to load and run my programs. I also ran some arm (4K pages) 
> > programs, which worked fine.
> 
> 0x37 is TT_PRIV_ACT, taken when privileged instructions are executed
> in unprivileged mode. Could you try running this program again with -d
> in_asm,op and see what is the faulting instruction and the generated
> ops? Maybe some instruction has too strict checks.

Sure. I pasted info from the error and fron the last TB.

Best regards
-- 
Edgar E. Iglesias
Axis Communications AB


% ./sparc64-linux-user/qemu-sparc64 -L /usr/sparc64-unknown-linux-gnu/ -d 
in_asm,op ~/ctest.sparc64.shared 
Unhandled trap: 0x37
pc: 00000000b5c51734  npc: 00000000b5c51738
General Registers:
%g0: 0000000000000000   %g1: 00000000b7cbcbc8   %g2: 0000000000000001   %g3: 
0000000000000060
%g4: 00000000b5d584c8   %g5: 0000000000000000   %g6: 00000000000001c0   %g7: 
0000000000000000
Current Register Window:
%o0: 00000000b5d58500   %o1: 00000000b7cbca00   %o2: 0000000000000010   %o3: 
0000000000000000
%o4: 0000000000000000   %o5: 0000000000000000   %o6: 00000000b7cbbfb1   %o7: 
00000000b5c3fca4
%l0: 00000000b5d58120   %l1: 0000000000000000   %l2: 0000000000000000   %l3: 
0000000000000c00
%l4: 0000000000000000   %l5: 0000000000000000   %l6: 0000000000000000   %l7: 
00000000b5d57310
%i0: 00000000b7cbce70   %i1: 00000000b7cbc990   %i2: 00000000b5c3c298   %i3: 
00000000b5c3c000
%i4: 0000000000000000   %i5: 0000000000000000   %i6: 00000000b7cbc081   %i7: 
00000000b5c404cc

Floating Point Registers:
%f00: 000000000.000000 000000000.000000 000000000.000000 000000000.000000
%f04: 000000000.000000 000000000.000000 000000000.000000 000000000.000000
%f08: 000000000.000000 000000000.000000 000000000.000000 000000000.000000
%f12: 000000000.000000 000000000.000000 000000000.000000 000000000.000000
%f16: 000000000.000000 000000000.000000 000000000.000000 000000000.000000
%f20: 000000000.000000 000000000.000000 000000000.000000 000000000.000000
%f24: 000000000.000000 000000000.000000 000000000.000000 000000000.000000
%f28: 000000000.000000 000000000.000000 000000000.000000 000000000.000000
pstate: 0x00000092 ccr: 0x00 asi: 0x00 tl: 0 fprs: 0
cansave: 4 canrestore: 2 otherwin: 0 wstate 0 cleanwin 6 cwp 1
fsr: 0x00000000


start    end      size     prot
00100000-00102000 00002000 r-x
00200000-00202000 00002000 rwx
b5c3c000-b5c58000 0001c000 r-x
b5c58000-b5d56000 000fe000 ---
b5d56000-b5d5a000 00004000 rwx
b5d5a000-b7c3c000 01ee2000 ---
b7c3e000-b7cbe000 00080000 rw-
b7cbe000-b7cc0000 00002000 ---
start_brk   0x00200c58
end_code    0x00200c50
start_code  0x00100000
start_data  0x00200c50
end_data    0x00200c50
start_stack 0xb7cbce70
brk         0x00200c58
entry       0xb5c3f260
--------------

[cut]

--------------
IN: 
0x00000000b5c516f4:  membar  #StoreStore|#LoadStore|#StoreLoad
0x00000000b5c516f8:  wr  %g0, 0xf0, %asi
0x00000000b5c516fc:  subcc  %o2, 0x40, %g6
0x00000000b5c51700:  mov  %o1, %g1
0x00000000b5c51704:  andncc  %g6, 0x3f, %g6
0x00000000b5c51708:  srl  %g1, 3, %g2
0x00000000b5c5170c:  sub  %o2, %g6, %g3
0x00000000b5c51710:  andn  %o1, 0x3f, %o1
0x00000000b5c51714:  and  %g2, 7, %g2
0x00000000b5c51718:  andncc  %g3, 7, %g3
0x00000000b5c5171c:  fmovd  %f0, %f2
0x00000000b5c51720:  sub  %g3, 0x10, %g3
0x00000000b5c51724:  sub  %o2, %g6, %o2
0x00000000b5c51728:  alignaddr  %g1, %g0, %g0
0x00000000b5c5172c:  add  %g1, %g6, %g1
0x00000000b5c51730:  subcc  %o2, %g3, %o2
0x00000000b5c51734:  ldda  [ %o1 ] %asi, %f0
0x00000000b5c51738:  add  %g1, %g3, %g1
0x00000000b5c5173c:  ldda  [ %o1 + 0x40 ] %asi, %f16
0x00000000b5c51740:  sub  %g6, 0x80, %g6
0x00000000b5c51744:  ldda  [ %o1 + 0x80 ] %asi, %f32
0x00000000b5c51748:  rd  %pc, %g5
0x00000000b5c5174c:  addcc  %g5, 0xb8, %g5
0x00000000b5c51750:  sll  %g2, 9, %g2
0x00000000b5c51754:  jmp  %g5 + %g2
0x00000000b5c51758:  addcc  %o1, 0xc0, %o1

OP:
0x0000: movl_T0_im 0x0
0x0001: movl_T1_sim 0xf0
0x0002: movl_env_T0 0x9364
0x0003: movl_T0_o2
0x0004: movl_T1_sim 0x40
0x0005: sub_T1_T0_cc
0x0006: movl_g6_T0
0x0007: movl_T1_o1
0x0008: movl_g1_T1
0x0009: movl_T0_g6
0x000a: movl_T1_sim 0x3f
0x000b: andn_T1_T0
0x000c: logic_T0_cc
0x000d: movl_g6_T0
0x000e: movl_T0_g1
0x000f: movl_T1_sim 0x3
0x0010: srl
0x0011: movl_g2_T0
0x0012: movl_T0_o2
0x0013: movl_T1_g6
0x0014: sub_T1_T0
0x0015: movl_g3_T0
0x0016: movl_T0_o1
0x0017: movl_T1_sim 0x3f
0x0018: andn_T1_T0
0x0019: movl_o1_T0
0x001a: movl_T0_g2
0x001b: movl_T1_sim 0x7
0x001c: and_T1_T0
0x001d: movl_g2_T0
0x001e: movl_T0_g3
0x001f: movl_T1_sim 0x7
0x0020: andn_T1_T0
0x0021: logic_T0_cc
0x0022: movl_g3_T0
0x0023: clear_ieee_excp_and_FTT
0x0024: load_fpr_DT0_fprf0
0x0025: store_DT0_fpr_fprf2
0x0026: movl_T0_g3
0x0027: movl_T1_sim 0x10
0x0028: sub_T1_T0
0x0029: movl_g3_T0
0x002a: movl_T0_o2
0x002b: movl_T1_g6
0x002c: sub_T1_T0
0x002d: movl_o2_T0
0x002e: movl_T0_g1
0x002f: movl_T1_im 0x0
0x0030: alignaddr
0x0031: movl_T0_g1
0x0032: movl_T1_g6
0x0033: add_T1_T0
0x0034: movl_g1_T0
0x0035: movl_T0_o2
0x0036: movl_T1_g3
0x0037: sub_T1_T0_cc
0x0038: movl_o2_T0
0x0039: jmp_im 0xb5c51734
0x003a: movl_npc_im 0xb5c51738
0x003b: movl_T0_o1
0x003c: check_align_T0_7
0x003d: ld_asi_reg 0x0 0x8 0x0
0x003e: movl_T0_g1
0x003f: movl_T1_g3
0x0040: add_T1_T0
0x0041: movl_g1_T0
0x0042: jmp_im 0xb5c5173c
0x0043: movl_npc_im 0xb5c51740
0x0044: movl_T0_o1
0x0045: movl_T1_sim 0x40
0x0046: add_T1_T0
0x0047: check_align_T0_7
0x0048: ld_asi_reg 0x40 0x8 0x0
0x0049: movl_T0_g6
0x004a: movl_T1_sim 0x80
0x004b: sub_T1_T0
0x004c: movl_g6_T0
0x004d: jmp_im 0xb5c51744
0x004e: movl_npc_im 0xb5c51748
0x004f: movl_T0_o1
0x0050: movl_T1_sim 0x80
0x0051: add_T1_T0
0x0052: check_align_T0_7
0x0053: ld_asi_reg 0x0 0x8 0x0
0x0054: movl_T0_im 0xb5c51748
0x0055: movl_g5_T0
0x0056: movl_T0_g5
0x0057: movl_T1_sim 0xb8
0x0058: add_T1_T0_cc
0x0059: movl_g5_T0
0x005a: movl_T0_g2
0x005b: movl_T1_sim 0x9
0x005c: sll
0x005d: movl_g2_T0
0x005e: movl_T0_g5
0x005f: movl_T1_g2
0x0060: add_T1_T0
0x0061: check_align_T0_3
0x0062: movl_npc_T0
0x0063: movl_T0_o1
0x0064: movl_T1_sim 0xc0
0x0065: add_T1_T0_cc
0x0066: movl_o1_T0
0x0067: next_insn
0x0068: movl_T0_0
0x0069: exit_tb
0x006a: end