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[Qemu-devel] [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers d
From: |
Jan Kiszka |
Subject: |
[Qemu-devel] [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically |
Date: |
Mon, 17 Nov 2008 17:18:59 +0100 |
User-agent: |
StGIT/0.14.2 |
Commit 5459 broke gdbstub's dynamic register set switching between
x86-64 and i386. That prevents setting the correct architecture in gdb
when debugging 32 or 16-bit code in a 64-bit emulator. This patch
reintroduces the feature over previous refactorings.
Signed-off-by: Jan Kiszka <address@hidden>
---
gdbstub.c | 50 +++++++++++++++++++++++++++++++++++++-------------
target-i386/cpu.h | 7 +++++--
2 files changed, 42 insertions(+), 15 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index c83b76a..2ed1695 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -301,8 +301,9 @@ static const int gpr_map[16] = {
8, 9, 10, 11, 12, 13, 14, 15
};
#else
-static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
+#define gpr_map gpr_map32
#endif
+static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
@@ -316,7 +317,10 @@ static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
{
if (n < CPU_NB_REGS) {
- GET_REGL(env->regs[gpr_map[n]]);
+ if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK))
+ GET_REGL(env->regs[gpr_map[n]]);
+ else if (n < CPU_NB_REGS32)
+ GET_REG32(env->regs[gpr_map32[n]]);
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
#ifdef USE_X86LDOUBLE
/* FIXME: byteswap float values - after fixing fpregs layout. */
@@ -327,12 +331,19 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t
*mem_buf, int n)
return 10;
} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
n -= IDX_XMM_REGS;
- stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
- stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
- return 16;
+ if (n < CPU_NB_REGS32
+ || (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK))) {
+ stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
+ stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
+ return 16;
+ }
} else {
switch (n) {
- case IDX_IP_REG: GET_REGL(env->eip);
+ case IDX_IP_REG:
+ if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK))
+ GET_REG64(env->eip);
+ else
+ GET_REG32(env->eip);
case IDX_FLAGS_REG: GET_REG32(env->eflags);
case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
@@ -400,8 +411,13 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t
*mem_buf, int n)
uint32_t tmp;
if (n < CPU_NB_REGS) {
- env->regs[gpr_map[n]] = ldtul_p(mem_buf);
- return sizeof(target_ulong);
+ if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)) {
+ env->regs[gpr_map[n]] = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ } else if (n < CPU_NB_REGS32) {
+ env->regs[gpr_map32[n]] = ldl_p(mem_buf);
+ return 4;
+ }
} else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
#ifdef USE_X86LDOUBLE
/* FIXME: byteswap float values - after fixing fpregs layout. */
@@ -410,14 +426,22 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t
*mem_buf, int n)
return 10;
} else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
n -= IDX_XMM_REGS;
- env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
- env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
- return 16;
+ if (n < CPU_NB_REGS32
+ || (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK))) {
+ env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
+ env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
+ return 16;
+ }
} else {
switch (n) {
case IDX_IP_REG:
- env->eip = ldtul_p(mem_buf);
- return sizeof(target_ulong);
+ if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)) {
+ env->eip = ldq_p(mem_buf);
+ return 8;
+ } else {
+ env->eip = ldl_p(mem_buf);
+ return 4;
+ }
case IDX_FLAGS_REG:
env->eflags = ldl_p(mem_buf);
return 4;
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index b7c8a2f..01884ec 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -511,10 +511,13 @@ typedef union {
#endif
#define MMX_Q(n) q
+#define CPU_NB_REGS64 16
+#define CPU_NB_REGS32 8
+
#ifdef TARGET_X86_64
-#define CPU_NB_REGS 16
+#define CPU_NB_REGS CPU_NB_REGS64
#else
-#define CPU_NB_REGS 8
+#define CPU_NB_REGS CPU_NB_REGS32
#endif
#define NB_MMU_MODES 2
- [Qemu-devel] [PATCH v5 15/18] gdbstub: Add vCont support, (continued)
- [Qemu-devel] [PATCH v5 01/18] Convert CPU_PC_FROM_TB to static inline, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 06/18] Respect length of watchpoints, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 14/18] x86: Dump debug registers, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 11/18] Add debug exception hook, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 10/18] Introduce BP_WATCHPOINT_HIT flag, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically,
Jan Kiszka <=
- Re: [Qemu-devel] [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Anthony Liguori, 2008/11/18
- Re: [Qemu-devel] [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Anthony Liguori, 2008/11/18
- Re: [Qemu-devel] [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Anthony Liguori, 2008/11/18
- [Qemu-devel] Re: [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Jan Kiszka, 2008/11/18
- Re: [Qemu-devel] Re: [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Paul Brook, 2008/11/18
- Re: [Qemu-devel] Re: [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Jan Kiszka, 2008/11/18
- Re: [Qemu-devel] Re: [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Paul Brook, 2008/11/18
- Re: [Qemu-devel] Re: [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Jan Kiszka, 2008/11/18
- Re: [Qemu-devel] Re: [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Paul Brook, 2008/11/18
- [Qemu-devel] Re: [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Jan Kiszka, 2008/11/19