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[Qemu-devel] [PATCH 13/14] pcbios: change acpi dsdt for q35 chipset.
From: |
Isaku Yamahata |
Subject: |
[Qemu-devel] [PATCH 13/14] pcbios: change acpi dsdt for q35 chipset. |
Date: |
Wed, 30 Sep 2009 19:18:48 +0900 |
change acpi dsdt for q35 chipset.
Signed-off-by: Isaku Yamahata <address@hidden>
---
Makefile | 2 +-
acpi-dsdt.dsl | 689 +++++++++++++++++++++++++++------------------------------
2 files changed, 327 insertions(+), 364 deletions(-)
diff --git a/Makefile b/Makefile
index 82bf1e8..0f99418 100644
--- a/Makefile
+++ b/Makefile
@@ -90,7 +90,7 @@ rombios32.o: rombios32.c acpi-dsdt.hex mcfg.h
$(GCC32) -O2 -Wall -I. -c -o $@ $<
acpi-dsdt.hex: acpi-dsdt.dsl
- $(CPP) -P $< > acpi-dsdt.dsl.i
+ $(CPP) -x assembler-with-cpp -P $< > acpi-dsdt.dsl.i
$(IASL) -tc -p $@ acpi-dsdt.dsl.i || ($(RM) $@; exit 1)
$(RM) acpi-dsdt.dsl.i
sed -i -e's/^unsigned/const unsigned/' $@
diff --git a/acpi-dsdt.dsl b/acpi-dsdt.dsl
index 56fb787..d75927b 100644
--- a/acpi-dsdt.dsl
+++ b/acpi-dsdt.dsl
@@ -27,19 +27,56 @@ DefinitionBlock (
{
Scope (\)
{
- /* Debug Output */
- OperationRegion (DBG, SystemIO, 0xb044, 0x04)
+ /* Debug Output. 0xb044 is already used by ich9 lpc.
+ so 0xb080 is chosen. */
+ OperationRegion (DBG, SystemIO, 0xb080, 0x04)
Field (DBG, DWordAcc, NoLock, Preserve)
{
DBGL, 32,
}
+
+ /* reserve this io port for gurest OS not to use it */
+ Device (DBG0)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_CRS, ResourceTemplate() {
+ IO (Decode16, 0xb080, 0xb080, 0x00, 0x04)
+ })
+ }
}
+ Scope (\_SB)
+ {
+ OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32,
+ B0EJ, 32,
+ }
+ OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
+ Field (PCSB, AnyAcc, NoLock, WriteAsZeros)
+ {
+ PCIB, 8,
+ }
+
+ /* reserve those io ports for gurest OS not to use it */
+ Device(HP0)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_CRS, ResourceTemplate() {
+ IO (Decode16, 0xae00, 0xae00, 0x00, 0x0C)
+ IO (Decode16, 0xae0c, 0xae0c, 0x00, 0x01)
+ })
+ }
+ }
+
/* PCI Bus definition */
Scope(\_SB) {
Device(PCI0) {
- Name (_HID, EisaId ("PNP0A03"))
+ Name (_HID, EisaId ("PNP0A08"))
+ Name (_CID, EisaId ("PNP0A03"))
Name (_ADR, 0x00)
Name (_UID, 1)
Name(_PRT, Package() {
@@ -53,98 +90,97 @@ DefinitionBlock (
Package() { nr##ffff, 2, lnk2, 0 }, \
Package() { nr##ffff, 3, lnk3, 0 }
-#define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
-#define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
-#define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
-#define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
- prt_slot0(0x0000),
- prt_slot1(0x0001),
- prt_slot2(0x0002),
- prt_slot3(0x0003),
- prt_slot0(0x0004),
- prt_slot1(0x0005),
- prt_slot2(0x0006),
- prt_slot3(0x0007),
- prt_slot0(0x0008),
- prt_slot1(0x0009),
- prt_slot2(0x000a),
- prt_slot3(0x000b),
- prt_slot0(0x000c),
- prt_slot1(0x000d),
- prt_slot2(0x000e),
- prt_slot3(0x000f),
- prt_slot0(0x0010),
- prt_slot1(0x0011),
- prt_slot2(0x0012),
- prt_slot3(0x0013),
- prt_slot0(0x0014),
- prt_slot1(0x0015),
- prt_slot2(0x0016),
- prt_slot3(0x0017),
- prt_slot0(0x0018),
- prt_slot1(0x0019),
- prt_slot2(0x001a),
- prt_slot3(0x001b),
- prt_slot0(0x001c),
- prt_slot1(0x001d),
- prt_slot2(0x001e),
- prt_slot3(0x001f),
+#define prt_slotD(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
+#define prt_slotA(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slotB(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slotC(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
+
+#define prt_slots(w, x, y, z) \
+ prt_slot##w(0x0000), \
+ prt_slot##x(0x0001), \
+ prt_slot##y(0x0002), \
+ prt_slot##z(0x0003), \
+ prt_slot##w(0x0004), \
+ prt_slot##x(0x0005), \
+ prt_slot##y(0x0006), \
+ prt_slot##z(0x0007), \
+ prt_slot##w(0x0008), \
+ prt_slot##x(0x0009), \
+ prt_slot##y(0x000a), \
+ prt_slot##z(0x000b), \
+ prt_slot##w(0x000c), \
+ prt_slot##x(0x000d), \
+ prt_slot##y(0x000e), \
+ prt_slot##z(0x000f), \
+ prt_slot##w(0x0010), \
+ prt_slot##x(0x0011), \
+ prt_slot##y(0x0012), \
+ prt_slot##z(0x0013), \
+ prt_slot##w(0x0014), \
+ prt_slot##x(0x0015), \
+ prt_slot##y(0x0016), \
+ prt_slot##z(0x0017), \
+ prt_slot##w(0x0018), \
+ prt_slot##x(0x0019), \
+ prt_slot##y(0x001a), \
+ prt_slot##z(0x001b), \
+ prt_slot##w(0x001c), \
+ prt_slot##x(0x001d), \
+ prt_slot##y(0x001e), \
+ prt_slot##z(0x001f),
+
+ prt_slots(D, A, B, C)
})
- OperationRegion(PCST, SystemIO, 0xae00, 0x08)
- Field (PCST, DWordAcc, NoLock, WriteAsZeros)
- {
- PCIU, 32,
- PCID, 32,
+#define hotplug_slot(name, nr, bus) \
+ Device (S##name) { \
+ Name (_ADR, nr##0000) \
+ Method (_EJ0,1) { \
+ Store(bus, \_SB.PCIB) \
+ Store(ShiftLeft(1, nr), \_SB.B0EJ) \
+ Return (0x0) \
+ } \
+ Name (_SUN, name) \
}
- OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
- Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
- {
- B0EJ, 32,
- }
-
-#define hotplug_slot(name, nr) \
- Device (S##name) { \
- Name (_ADR, nr##0000) \
- Method (_EJ0,1) { \
- Store(ShiftLeft(1, nr), B0EJ) \
- Return (0x0) \
- } \
- Name (_SUN, name) \
- }
-
- hotplug_slot(1, 0x0001)
- hotplug_slot(2, 0x0002)
- hotplug_slot(3, 0x0003)
- hotplug_slot(4, 0x0004)
- hotplug_slot(5, 0x0005)
- hotplug_slot(6, 0x0006)
- hotplug_slot(7, 0x0007)
- hotplug_slot(8, 0x0008)
- hotplug_slot(9, 0x0009)
- hotplug_slot(10, 0x000a)
- hotplug_slot(11, 0x000b)
- hotplug_slot(12, 0x000c)
- hotplug_slot(13, 0x000d)
- hotplug_slot(14, 0x000e)
- hotplug_slot(15, 0x000f)
- hotplug_slot(16, 0x0010)
- hotplug_slot(17, 0x0011)
- hotplug_slot(18, 0x0012)
- hotplug_slot(19, 0x0013)
- hotplug_slot(20, 0x0014)
- hotplug_slot(21, 0x0015)
- hotplug_slot(22, 0x0016)
- hotplug_slot(23, 0x0017)
- hotplug_slot(24, 0x0018)
- hotplug_slot(25, 0x0019)
- hotplug_slot(26, 0x001a)
- hotplug_slot(27, 0x001b)
- hotplug_slot(28, 0x001c)
- hotplug_slot(29, 0x001d)
- hotplug_slot(30, 0x001e)
- hotplug_slot(31, 0x001f)
+#define hotplug_slots1(bus) \
+ hotplug_slot(1, 0x0001, bus) \
+ hotplug_slot(2, 0x0002, bus) \
+ hotplug_slot(3, 0x0003, bus) \
+ hotplug_slot(4, 0x0004, bus) \
+ hotplug_slot(5, 0x0005, bus) \
+ hotplug_slot(6, 0x0006, bus) \
+ hotplug_slot(7, 0x0007, bus) \
+ hotplug_slot(8, 0x0008, bus) \
+ hotplug_slot(9, 0x0009, bus) \
+ hotplug_slot(10, 0x000a, bus) \
+ hotplug_slot(11, 0x000b, bus) \
+ hotplug_slot(12, 0x000c, bus) \
+ hotplug_slot(13, 0x000d, bus) \
+ hotplug_slot(14, 0x000e, bus) \
+ hotplug_slot(15, 0x000f, bus) \
+ hotplug_slot(16, 0x0010, bus) \
+ hotplug_slot(17, 0x0011, bus) \
+ hotplug_slot(18, 0x0012, bus) \
+ hotplug_slot(19, 0x0013, bus) \
+ hotplug_slot(20, 0x0014, bus) \
+ hotplug_slot(21, 0x0015, bus) \
+ hotplug_slot(22, 0x0016, bus) \
+ hotplug_slot(23, 0x0017, bus) \
+ hotplug_slot(24, 0x0018, bus) \
+ hotplug_slot(25, 0x0019, bus) \
+ hotplug_slot(26, 0x001a, bus) \
+ hotplug_slot(27, 0x001b, bus) \
+ hotplug_slot(28, 0x001c, bus) \
+ hotplug_slot(29, 0x001d, bus) \
+ hotplug_slot(30, 0x001e, bus) \
+ hotplug_slot(31, 0x001f, bus)
+
+#define hotplug_slots(bus) \
+ hotplug_slot(0, 0x0000, bus) \
+ hotplug_slots1(bus)
+
+ hotplug_slots1(0)
Name (_CRS, ResourceTemplate ()
{
@@ -191,26 +227,6 @@ DefinitionBlock (
,, , AddressRangeMemory, TypeStatic)
})
}
-#ifdef BX_QEMU
- Device(HPET) {
- Name(_HID, EISAID("PNP0103"))
- Name(_UID, 0)
- Method (_STA, 0, NotSerialized) {
- Return(0x0F)
- }
- Name(_CRS, ResourceTemplate() {
- DWordMemory(
- ResourceConsumer, PosDecode, MinFixed, MaxFixed,
- NonCacheable, ReadWrite,
- 0x00000000,
- 0xFED00000,
- 0xFED003FF,
- 0x00000000,
- 0x00000400 /* 1K memory: FED00000 - FED003FF */
- )
- })
- }
-#endif
}
Scope(\_SB.PCI0) {
@@ -230,13 +246,68 @@ DefinitionBlock (
}
}
- /* PIIX3 ISA bridge */
- Device (ISA) {
- Name (_ADR, 0x00010000)
- /* PIIX PCI to ISA irq remapping */
- OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ /* PCI D31:f0 LPC ISA bridge */
+ Device (LPC) {
+ /* PCI D31:f0 */
+ Name (_ADR, 0x001f0000)
+
+ /* ICH9 PCI to ISA irq remapping */
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ Field (PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ OperationRegion (LPCD, PCI_Config, 0x80, 0x2)
+ Field (LPCD, AnyAcc, NoLock, Preserve)
+ {
+ COMA, 3,
+ , 1,
+ COMB, 3,
+
+ Offset(0x01),
+ LPTD, 2,
+ , 2,
+ FDCD, 2
+ }
+ OperationRegion (LPCE, PCI_Config, 0x82, 0x2)
+ Field (LPCE, AnyAcc, NoLock, Preserve)
+ {
+ CAEN, 1,
+ CBEN, 1,
+ LPEN, 1,
+ FDEN, 1
+ }
+ /* High Precision Event Timer */
+ Device(HPET) {
+ Name(_HID, EISAID("PNP0103"))
+ Name(_UID, 0)
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ Name(_CRS, ResourceTemplate() {
+ DWordMemory(
+ ResourceConsumer, PosDecode, MinFixed, MaxFixed,
+ NonCacheable, ReadWrite,
+ 0x00000000,
+ 0xFED00000,
+ 0xFED003FF,
+ 0x00000000,
+ 0x00000400 /* 1K memory: FED00000 - FED003FF */
+ )
+ })
+ }
/* Real-time clock */
Device (RTC)
{
@@ -306,7 +377,15 @@ DefinitionBlock (
Name (_HID, EisaId ("PNP0700"))
Method (_STA, 0, NotSerialized)
{
- Return (0x0F)
+ Store (\_SB.PCI0.LPC.FDEN, Local0)
+ If (LEqual (Local0, 0))
+ {
+ Return (0x00)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
}
Method (_CRS, 0, NotSerialized)
{
@@ -327,8 +406,7 @@ DefinitionBlock (
Name (_HID, EisaId ("PNP0400"))
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSA, Local0)
- And (Local0, 0x80000000, Local0)
+ Store (\_SB.PCI0.LPC.LPEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -356,8 +434,7 @@ DefinitionBlock (
Name (_UID, 0x01)
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSC, Local0)
- And (Local0, 0x08000000, Local0)
+ Store (\_SB.PCI0.LPC.CAEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -384,8 +461,7 @@ DefinitionBlock (
Name (_UID, 0x02)
Method (_STA, 0, NotSerialized)
{
- Store (\_SB.PCI0.PX13.DRSC, Local0)
- And (Local0, 0x80000000, Local0)
+ Store (\_SB.PCI0.LPC.CBEN, Local0)
If (LEqual (Local0, 0))
{
Return (0x00)
@@ -406,217 +482,88 @@ DefinitionBlock (
}
}
}
+ }
- /* PIIX4 PM */
- Device (PX13) {
- Name (_ADR, 0x00010003)
+ /* PCI to PCI Bridge on bus 0*/
+ Scope (\_SB.PCI0) {
+ Device (PCI6) {
+ Name (_ADR, 0x1e0000) /* 0:1e.00 */
+ Name (_UID, 6)
+ Name (_PRT, Package() {
+ prt_slots(A, B, C, D)
+ })
+ hotplug_slots(6)
+ }
+ }
- OperationRegion (P13C, PCI_Config, 0x5c, 0x24)
- Field (P13C, DWordAcc, NoLock, Preserve)
- {
- DRSA, 32,
- DRSB, 32,
- DRSC, 32,
- DRSE, 32,
- DRSF, 32,
- DRSG, 32,
- DRSH, 32,
- DRSI, 32,
- DRSJ, 32
- }
- }
+#define pci_bridge(dev, uid, bus, w, x, y, z) \
+ Scope (\_SB.PCI0.PCI6) { \
+ Device (PCI##uid) { \
+ Name (_ADR, 0x##dev##0000) \
+ Name (_UID, uid) \
+ Name (_PRT, Package() { \
+ prt_slots(w, x, y, z) \
+ }) \
+ hotplug_slots(bus) \
+ } \
}
+ pci_bridge(1d, 0, 7, A, B, C, D)
+ pci_bridge(1e, 1, 8, B, C, D, A)
+ pci_bridge(1f, 2, 9, C, D, A, B)
+
/* PCI IRQs */
Scope(\_SB) {
- Field (\_SB.PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
- {
- PRQ0, 8,
- PRQ1, 8,
- PRQ2, 8,
- PRQ3, 8
- }
-
- Device(LNKA){
- Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
- Name(_UID, 1)
- Name(_PRS, ResourceTemplate(){
- Interrupt (, Level, ActiveHigh, Shared)
- { 5, 10, 11 }
- })
- Method (_STA, 0, NotSerialized)
- {
- Store (0x0B, Local0)
- If (And (0x80, PRQ0, Local1))
- {
- Store (0x09, Local0)
- }
- Return (Local0)
- }
- Method (_DIS, 0, NotSerialized)
- {
- Or (PRQ0, 0x80, PRQ0)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (PRR0, ResourceTemplate ()
- {
- Interrupt (, Level, ActiveHigh, Shared)
- {1}
- })
- CreateDWordField (PRR0, 0x05, TMP)
- Store (PRQ0, Local0)
- If (LLess (Local0, 0x80))
- {
- Store (Local0, TMP)
- }
- Else
- {
- Store (Zero, TMP)
- }
- Return (PRR0)
- }
- Method (_SRS, 1, NotSerialized)
- {
- CreateDWordField (Arg0, 0x05, TMP)
- Store (TMP, PRQ0)
- }
- }
- Device(LNKB){
- Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
- Name(_UID, 2)
- Name(_PRS, ResourceTemplate(){
- Interrupt (, Level, ActiveHigh, Shared)
- { 5, 10, 11 }
- })
- Method (_STA, 0, NotSerialized)
- {
- Store (0x0B, Local0)
- If (And (0x80, PRQ1, Local1))
- {
- Store (0x09, Local0)
- }
- Return (Local0)
- }
- Method (_DIS, 0, NotSerialized)
- {
- Or (PRQ1, 0x80, PRQ1)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (PRR0, ResourceTemplate ()
- {
- Interrupt (, Level, ActiveHigh, Shared)
- {1}
- })
- CreateDWordField (PRR0, 0x05, TMP)
- Store (PRQ1, Local0)
- If (LLess (Local0, 0x80))
- {
- Store (Local0, TMP)
- }
- Else
- {
- Store (Zero, TMP)
- }
- Return (PRR0)
- }
- Method (_SRS, 1, NotSerialized)
- {
- CreateDWordField (Arg0, 0x05, TMP)
- Store (TMP, PRQ1)
- }
- }
- Device(LNKC){
- Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
- Name(_UID, 3)
- Name(_PRS, ResourceTemplate(){
- Interrupt (, Level, ActiveHigh, Shared)
- { 5, 10, 11 }
- })
- Method (_STA, 0, NotSerialized)
- {
- Store (0x0B, Local0)
- If (And (0x80, PRQ2, Local1))
- {
- Store (0x09, Local0)
- }
- Return (Local0)
- }
- Method (_DIS, 0, NotSerialized)
- {
- Or (PRQ2, 0x80, PRQ2)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (PRR0, ResourceTemplate ()
- {
- Interrupt (, Level, ActiveHigh, Shared)
- {1}
- })
- CreateDWordField (PRR0, 0x05, TMP)
- Store (PRQ2, Local0)
- If (LLess (Local0, 0x80))
- {
- Store (Local0, TMP)
- }
- Else
- {
- Store (Zero, TMP)
- }
- Return (PRR0)
- }
- Method (_SRS, 1, NotSerialized)
- {
- CreateDWordField (Arg0, 0x05, TMP)
- Store (TMP, PRQ2)
- }
- }
- Device(LNKD){
- Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
- Name(_UID, 4)
- Name(_PRS, ResourceTemplate(){
- Interrupt (, Level, ActiveHigh, Shared)
- { 5, 10, 11 }
- })
- Method (_STA, 0, NotSerialized)
- {
- Store (0x0B, Local0)
- If (And (0x80, PRQ3, Local1))
- {
- Store (0x09, Local0)
- }
- Return (Local0)
- }
- Method (_DIS, 0, NotSerialized)
- {
- Or (PRQ3, 0x80, PRQ3)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (PRR0, ResourceTemplate ()
- {
- Interrupt (, Level, ActiveHigh, Shared)
- {1}
- })
- CreateDWordField (PRR0, 0x05, TMP)
- Store (PRQ3, Local0)
- If (LLess (Local0, 0x80))
- {
- Store (Local0, TMP)
- }
- Else
- {
- Store (Zero, TMP)
- }
- Return (PRR0)
- }
- Method (_SRS, 1, NotSerialized)
- {
- CreateDWordField (Arg0, 0x05, TMP)
- Store (TMP, PRQ3)
- }
+#define define_link(link, uid, reg) \
+ Device(link){ \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, uid) \
+ Name(_PRS, ResourceTemplate(){ \
+ Interrupt (, Level, ActiveHigh, \
+ Shared) \
+ { 5, 10, 11 } \
+ }) \
+ Method (_STA, 0, NotSerialized) \
+ { \
+ Store (0x0B, Local0) \
+ If (And (0x80, reg, Local1)) \
+ { \
+ Store (0x09, Local0) \
+ } \
+ Return (Local0) \
+ } \
+ Method (_DIS, 0, NotSerialized) \
+ { \
+ Or (reg, 0x80, reg) \
+ } \
+ Method (_CRS, 0, NotSerialized) \
+ { \
+ Name (PRR0, ResourceTemplate () \
+ { \
+ Interrupt (, Level, ActiveHigh, \
+ Shared) \
+ {1} \
+ }) \
+ CreateDWordField (PRR0, 0x05, TMP) \
+ And (reg, 0x0F, Local0) \
+ Store (Local0, TMP) \
+ Return (PRR0) \
+ } \
+ Method (_SRS, 1, NotSerialized) \
+ { \
+ CreateDWordField (Arg0, 0x05, TMP) \
+ Store (TMP, reg) \
+ } \
}
+
+ define_link(LNKA, 0, \_SB.PCI0.LPC.PRQA)
+ define_link(LNKB, 1, \_SB.PCI0.LPC.PRQB)
+ define_link(LNKC, 2, \_SB.PCI0.LPC.PRQC)
+ define_link(LNKD, 3, \_SB.PCI0.LPC.PRQD)
+ define_link(LNKE, 4, \_SB.PCI0.LPC.PRQE)
+ define_link(LNKF, 5, \_SB.PCI0.LPC.PRQF)
+ define_link(LNKG, 6, \_SB.PCI0.LPC.PRQG)
+ define_link(LNKH, 7, \_SB.PCI0.LPC.PRQH)
}
/*
@@ -653,46 +600,62 @@ DefinitionBlock (
Return(0x01)
}
-#define gen_pci_hotplug(nr) \
- If (And(\_SB.PCI0.PCIU, ShiftLeft(1, nr))) { \
- Notify(\_SB.PCI0.S##nr, 1) \
+#define gen_pci_hotplug(nr, DEV) \
+ If (And(\_SB.PCIU, ShiftLeft(1, nr))) { \
+ Notify(DEV##.S##nr, 1) \
} \
- If (And(\_SB.PCI0.PCID, ShiftLeft(1, nr))) { \
- Notify(\_SB.PCI0.S##nr, 3) \
+ If (And(\_SB.PCID, ShiftLeft(1, nr))) { \
+ Notify(DEV##.S##nr, 3) \
}
+#define gen_pci_hotplug_1(DEV) \
+ gen_pci_hotplug(1, DEV) \
+ gen_pci_hotplug(2, DEV) \
+ gen_pci_hotplug(3, DEV) \
+ gen_pci_hotplug(4, DEV) \
+ gen_pci_hotplug(5, DEV) \
+ gen_pci_hotplug(6, DEV) \
+ gen_pci_hotplug(7, DEV) \
+ gen_pci_hotplug(8, DEV) \
+ gen_pci_hotplug(9, DEV) \
+ gen_pci_hotplug(10, DEV) \
+ gen_pci_hotplug(11, DEV) \
+ gen_pci_hotplug(12, DEV) \
+ gen_pci_hotplug(13, DEV) \
+ gen_pci_hotplug(14, DEV) \
+ gen_pci_hotplug(15, DEV) \
+ gen_pci_hotplug(16, DEV) \
+ gen_pci_hotplug(17, DEV) \
+ gen_pci_hotplug(18, DEV) \
+ gen_pci_hotplug(19, DEV) \
+ gen_pci_hotplug(20, DEV) \
+ gen_pci_hotplug(21, DEV) \
+ gen_pci_hotplug(22, DEV) \
+ gen_pci_hotplug(23, DEV) \
+ gen_pci_hotplug(24, DEV) \
+ gen_pci_hotplug(25, DEV) \
+ gen_pci_hotplug(26, DEV) \
+ gen_pci_hotplug(27, DEV) \
+ gen_pci_hotplug(28, DEV) \
+ gen_pci_hotplug(29, DEV) \
+ gen_pci_hotplug(30, DEV) \
+ gen_pci_hotplug(31, DEV)
+
+#define gen_pci_hotplugs1(DEV, bus) \
+ Store(bus, \_SB.PCIB) \
+ gen_pci_hotplug_1(DEV)
+
+#define gen_pci_hotplugs(DEV, bus) \
+ Store(bus, \_SB.PCIB) \
+ gen_pci_hotplug(0, DEV) \
+ gen_pci_hotplug_1(DEV)
+
Method(_L01) {
- gen_pci_hotplug(1)
- gen_pci_hotplug(2)
- gen_pci_hotplug(3)
- gen_pci_hotplug(4)
- gen_pci_hotplug(5)
- gen_pci_hotplug(6)
- gen_pci_hotplug(7)
- gen_pci_hotplug(8)
- gen_pci_hotplug(9)
- gen_pci_hotplug(10)
- gen_pci_hotplug(11)
- gen_pci_hotplug(12)
- gen_pci_hotplug(13)
- gen_pci_hotplug(14)
- gen_pci_hotplug(15)
- gen_pci_hotplug(16)
- gen_pci_hotplug(17)
- gen_pci_hotplug(18)
- gen_pci_hotplug(19)
- gen_pci_hotplug(20)
- gen_pci_hotplug(21)
- gen_pci_hotplug(22)
- gen_pci_hotplug(23)
- gen_pci_hotplug(24)
- gen_pci_hotplug(25)
- gen_pci_hotplug(26)
- gen_pci_hotplug(27)
- gen_pci_hotplug(28)
- gen_pci_hotplug(29)
- gen_pci_hotplug(30)
- gen_pci_hotplug(31)
+ gen_pci_hotplugs1(\_SB.PCI0, 0)
+ gen_pci_hotplugs(\_SB.PCI0.PCI6, 6)
+ gen_pci_hotplugs(\_SB.PCI0.PCI6.PCI0, 7)
+ gen_pci_hotplugs(\_SB.PCI0.PCI6.PCI1, 8)
+ gen_pci_hotplugs(\_SB.PCI0.PCI6.PCI2, 9)
Return (0x01)
--
1.6.0.2
- [Qemu-devel] [PATCH 00/14] pcbios: support q35 chipset, Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 13/14] pcbios: change acpi dsdt for q35 chipset.,
Isaku Yamahata <=
- [Qemu-devel] [PATCH 09/14] pcbios: comment out PCI_FIXED_HOST_BRIDGE for gmch host pci bridge to undef., Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 06/14] pcbios: rombios32: make pci space assigner preferchable memory aware., Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 02/14] pcbios: fix makesym.perl, Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 14/14] pcibos/acpi dsdt: APIC mode support for q35 chipset, Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 08/14] pcibos: initialize q35 chipset., Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 01/14] pcbios: add generated files to dot gitignore., Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 03/14] pcbios: remove iasl output file when error., Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 05/14] pcbios: rombios32: make pci memory space assignment 64bit aware., Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 12/14] pcbios: make pci bar initialization to be aware of preferchable memory., Isaku Yamahata, 2009/09/30
- [Qemu-devel] [PATCH 07/14] pcbios: enable debug output for debug., Isaku Yamahata, 2009/09/30