Re: [Qemu-devel] Re: POST failure (loop) with isapc and seabios

[Sebastian Herbszt]

Gleb Natapov wrote:
> On Mon, Nov 23, 2009 at 10:30:56PM +0100, Sebastian Herbszt wrote:
> > Gleb Natapov wrote:
> > >On Mon, Nov 23, 2009 at 08:19:54PM +0100, Sebastian Herbszt wrote:
> > >>Gleb Natapov wrote:
> > >>>On Sun, Nov 22, 2009 at 09:01:45PM +0100, Sebastian Herbszt wrote:
> > >>>>Gleb Natapov wrote:
> > >>>>>On Sun, Nov 22, 2009 at 04:31:24PM +0100, Sebastian Herbszt wrote:
> > >>>>>>
> > >>>>>>Bad things could happen if someone modifies the BIOS because it's 
> > unprotected
> > >>>>>>(e.g. VM crash).
> > >>>>>>
> > >>>>>BIOS is reloaded during VM reset.
> > >>>>
> > >>>>The BIOS is not reloaded - tested with "reboot" on Linux and system_reset 
> > in monitor.
> > >>>>
> > >>>Looks like a bug. Tested with latest QEMU version I assume?
> > >>
> > >>Tested with v0.11.0-rc0-1677-gf165b53. Where do you suspect a bug? In the 
> > behaviour
> > >>on "reboot" or system_reset? I think it depends wheter it's a software or 
> > hardware reset.
> > >>
> > >The bug is that BIOS rom is not reloaded on hardware reset (what do you
> > >call software reset?). Can you retest with latest git?
> >
> > Same with v0.11.0-rc0-1699-gb0293e5.
> > Bochs has the notion of BX_RESET_SOFTWARE and BX_RESET_HARDWARE. Those
> > two describe the source of the reset and the hardware, in most cases just the 
> > cpu, is reset
> > differently depending on the source (e.g. hardware reset / power on vs. INIT#). 
> > I think this
> > behaviour is also described in the 440fx spec (chapter "4.5.3 SYSTEM RESET").
> >
> > If the monitor command "system_reset" is supposed to be the equivalent of 
> > pushing the reset
> > button of the box, then the bios should be reloaded (i think, not entirely sure 
> > what the pin is
> > wired to). But the bios should not be reloaded if the OS just jumps to the bios 
> > reset code.
> Correct, but modern OSes never jump to the bios reset code. They use
> ACPI reset, kbd reset or triple fault to do reset. All of those generate
> exactly the same kind of reset as "system_reset" monitor command.

With the 440FX you get two sources of a hard reset - power on and i/o write to 
reset control register.
Tho the PMC should not be used to generate a hard reset if used with a PIIX3. 
You get a soft reset on
CPU shutdown bus cycle, i/o write to keyboard controller, i/o write to port 92h 
and i/o write to reset
control register. The latter can be used for hard and soft resets. During a 
hard reset the PMC sets its
configuration registers to default values. The PAM registers are set to 0 and 
the BIOS is accessed thru
rom and not shadow ram. On a triple fault the CPU generates the shutdown bus 
cycle and since the PMC
responds to it with a soft reset the BIOS is not reloaded (?). I might have 
missed something in some
specification tho.

- Sebastian