Re: [Qemu-devel] [PATCH 09/10] target-alpha: Implement load-locked/store-conditional properly.

[Richard Henderson]

On 03/25/2010 10:40 AM, Blue Swirl wrote:
> Sparc V8 has two atomic instructions, ldstub and swap.

I know -- but not the CAS operation being discussed here.

As I think about this more and more, the Real Problem is
not with the CAS, but with the memory ordering requirements
of the guest vs the memory ordering of the host.  It's easy
to implement things on x86, because of the host's strict
memory ordering.  It would be much more difficult to properly
emulate x86 on a relaxed memory ordering host.  We'd need to
insert barriers between pairs of qemu_{ld,st} operations.

I may give this some proper thinking this weekend.


r~