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[Qemu-devel] [PATCH 16/18] tcg/arm: fix argument alignment in qemu_st64
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 16/18] tcg/arm: fix argument alignment in qemu_st64 |
Date: |
Wed, 7 Apr 2010 19:51:23 +0200 |
64-bit arguments should be aligned on an even register as specified
by the "Procedure Call Standard for the ARM Architecture".
Signed-off-by: Aurelien Jarno <address@hidden>
---
tcg/arm/tcg-target.c | 19 ++++++++++---------
1 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index a4419f8..91542bd 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1255,13 +1255,16 @@ static inline void tcg_out_qemu_st(TCGContext *s, const
TCGArg *args, int opc)
tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R2, 0, mem_index);
break;
case 3:
- tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
- TCG_REG_R1, 0, data_reg, SHIFT_IMM_LSL(0));
- if (data_reg2 != TCG_REG_R2) {
+ tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R8, 0, mem_index);
+ tcg_out32(s, (COND_AL << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
+ if (data_reg != TCG_REG_R2) {
tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
- TCG_REG_R2, 0, data_reg2, SHIFT_IMM_LSL(0));
+ TCG_REG_R2, 0, data_reg, SHIFT_IMM_LSL(0));
+ }
+ if (data_reg2 != TCG_REG_R3) {
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
+ TCG_REG_R3, 0, data_reg2, SHIFT_IMM_LSL(0));
}
- tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R3, 0, mem_index);
break;
}
# else
@@ -1300,10 +1303,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const
TCGArg *args, int opc)
tcg_out_bl(s, COND_AL, (tcg_target_long) qemu_st_helpers[s_bits] -
(tcg_target_long) s->code_ptr);
-# if TARGET_LONG_BITS == 64
if (opc == 3)
tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R13, TCG_REG_R13, 0x10);
-# endif
*label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
#else /* !CONFIG_SOFTMMU */
@@ -1709,7 +1710,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_qemu_st8, { "s", "s" } },
{ INDEX_op_qemu_st16, { "s", "s" } },
{ INDEX_op_qemu_st32, { "s", "s" } },
- { INDEX_op_qemu_st64, { "s", "S", "s" } },
+ { INDEX_op_qemu_st64, { "S", "S", "s" } },
#else
{ INDEX_op_qemu_ld8u, { "r", "l", "l" } },
{ INDEX_op_qemu_ld8s, { "r", "l", "l" } },
@@ -1721,7 +1722,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_qemu_st8, { "s", "s", "s" } },
{ INDEX_op_qemu_st16, { "s", "s", "s" } },
{ INDEX_op_qemu_st32, { "s", "s", "s" } },
- { INDEX_op_qemu_st64, { "s", "S", "s", "s" } },
+ { INDEX_op_qemu_st64, { "S", "S", "s", "s" } },
#endif
{ INDEX_op_bswap16_i32, { "r", "r" } },
--
1.7.0.4
- Re: [Qemu-devel] [PATCH 11/18] tcg/arm: add bswap ops, (continued)
- [Qemu-devel] [PATCH 08/18] tcg/arm: use the blx instruction when possible, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 06/18] tcg/arm: add defines for the allowed instructions set, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 03/18] tcg/arm: remove store signed functions, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 04/18] tcg/arm: replace integer values by registers enum, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 18/18] tcg/arm: don't try to load constants using pc, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 13/18] tcg/arm: use ext* ops in qemu_ld, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 10/18] tcg/arm: add ext16u op, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 16/18] tcg/arm: fix argument alignment in qemu_st64,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 17/18] tcg/arm: optimize register allocation order, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 14/18] tcg/arm: bswap arguments in qemu_ld/st if needed, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 15/18] tcg/arm: remove useless register tests in qemu_ld/st, Aurelien Jarno, 2010/04/07
- [Qemu-devel] [PATCH 12/18] tcg/arm: remove conditional argument for qemu_ld/st, Aurelien Jarno, 2010/04/07