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Re: [Qemu-devel] [PATCH 09/17] lm32: timer model
From: |
Michael Walle |
Subject: |
Re: [Qemu-devel] [PATCH 09/17] lm32: timer model |
Date: |
Fri, 11 Feb 2011 23:29:31 +0100 |
User-agent: |
KMail/1.13.5 (Linux/2.6.32-5-686-bigmem; KDE/4.4.5; i686; ; ) |
Am Freitag 11 Februar 2011, 22:22:32 schrieb Blue Swirl:
> > +static uint32_t timer_read(void *opaque, target_phys_addr_t addr)
> > +{
> > + LM32TimerState *s = opaque;
> > + uint32_t r = 0;
> > +
> > + addr >>= 2;
> > + switch (addr) {
> > + case R_SR:
> > + case R_CR:
> > + case R_PERIOD:
> > + r = s->regs[addr];
> > + break;
> > + case R_SNAPSHOT:
> > + r = (uint32_t)ptimer_get_count(s->ptimer);
> > + break;
> > +
> > + default:
> > + hw_error("lm32_timer: read access to unkown register 0x"
> > + TARGET_FMT_plx, addr << 2);
>
> Insecure, please fix also others.
Many devices in hw/ treat memory access to unknown registers in that way. Are
there any 'good' example models, where i can look at? I guess i should print a
warning instead?
--
Michael
- Re: [Qemu-devel] [PATCH 12/17] lm32: support for creating device tree, (continued)
[Qemu-devel] [PATCH 17/17] MAINTAINERS: add LatticeMico32 maintainer, Michael Walle, 2011/02/10
[Qemu-devel] [PATCH 14/17] lm32: todo and documentation, Michael Walle, 2011/02/10
[Qemu-devel] [PATCH 09/17] lm32: timer model, Michael Walle, 2011/02/10
[Qemu-devel] [PATCH 15/17] lm32: opcode testsuite, Michael Walle, 2011/02/10
[Qemu-devel] Re: [PATCH 00/17 v2] LatticeMico32 target, Edgar E. Iglesias, 2011/02/11