Re: [Qemu-devel] [PATCH] ioapic: Do not set irr for masked edge IRQs

[Aurelien Jarno]

On Tue, Apr 26, 2011 at 03:00:30PM +0200, Jan Kiszka wrote:
> On 2011-04-09 13:18, Jan Kiszka wrote:
> > From: Jan Kiszka <address@hidden>
> > 
> > So far we set IRR for edge IRQs even if the pin is masked. If the guest
> > later on unmasks and switches the pin to level-triggered mode, irr will
> > remain set, causing an IRQ storm. The point is that setting IRR is not
> > correct in this case according to the spec, and avoiding this resolves
> > the issue.
> > 
> > Reported-and-tested-by: Isaku Yamahata <address@hidden>
> > Signed-off-by: Jan Kiszka <address@hidden>
> > ---
> >  hw/ioapic.c |    5 +++--
> >  1 files changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/hw/ioapic.c b/hw/ioapic.c
> > index 569327d..6c26e82 100644
> > --- a/hw/ioapic.c
> > +++ b/hw/ioapic.c
> > @@ -160,8 +160,9 @@ static void ioapic_set_irq(void *opaque, int vector, 
> > int level)
> >                  s->irr &= ~mask;
> >              }
> >          } else {
> > -            /* edge triggered */
> > -            if (level) {
> > +            /* According to the 82093AA manual, we must ignore edge 
> > requests
> > +             * if the input pin is masked. */
> > +            if (level && !(entry & IOAPIC_LVT_MASKED)) {
> >                  s->irr |= mask;
> >                  ioapic_service(s);
> >              }
> 
> Ping?
> 

Done.


-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net